Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/302
H01L-021/461
출원번호
US-0731656
(2003-12-08)
발명자
/ 주소
Satta, Alessandra
Maex, Karen
Elers, Kai-Erik
Saanila, Ville Antero
Soininen, Pekka Juha
Haukka, Suvi P.
출원인 / 주소
Interuniversitair Nizroelecmica
ASM International NV
대리인 / 주소
Knobbe, Martens, Olson &
인용정보
피인용 횟수 :
41인용 특허 :
29
초록▼
Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the m
Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces with a barrier material. The selective formation allows the deposition to be “bottomless,” thus leaving the conductive material at a via bottom exposed for direct metal-to-metal contact when further conductive material is deposited into the opening after barrier formation on the insulating surfaces. Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls in the opening.
대표청구항▼
1. A method of selectively depositing a layer on a substrate comprising a first surface and a second surface, the method comprising:modifying the first surface; and selectively depositing a layer on the second surface relative to the first surface using an atomic layer deposition (ALD) process, wher
1. A method of selectively depositing a layer on a substrate comprising a first surface and a second surface, the method comprising:modifying the first surface; and selectively depositing a layer on the second surface relative to the first surface using an atomic layer deposition (ALD) process, wherein modifying the first surface blocks deposition by the ALD process. 2. The method of claim 1, wherein modifying the first surface comprises adsorption of a blocking substance that blocks growth by atomic layer deposition.3. The method of claim 2, further comprising removing the blocking substance from the first surface after selectively depositing the layer.4. The method of claim 1, wherein modifying the first surface comprises forming growth-blocking ligands on the first surface.5. The method of claim 4, wherein the growth-blocking ligands have the chemical formula SiXn, where X is selected from the group consisting of fluorine (F), chlorine (C1), bromine (Br) and iodine (I) and n is an integer selected from the group consisting of 1, 2 and 3.6. The method of claim 1, further comprising conditioning the second surface prior to modifying the first surface.7. The method of claim 1, further comprising conditioning the second surface after modifying the first surface and prior to selectively depositing the layer.8. A method of selectively depositing a layer on a substrate comprising:modifying a first surface of the substrate to prevent subsequent deposition of the layer thereon; and selectively coating over a second surface of the substrate as compared to the first surface by repeatedly alternating exposure of the substrate to at least two reactants, each alternating exposure having a self-limiting effect. 9. The method of claim 8 wherein the first surface comprises a conductor and the second surface comprises an insulating material that is selectively coated.10. The method of claim 9, wherein the second surface defines an opening in an insulating layer within an integrated circuit and the first surface comprises a metal element exposed by the opening.11. The method of claim 9, wherein selectively coating comprises depositing a barrier material over the insulating material.12. The method of claim 11, wherein the barrier material is conductive and has a resistivity less than about 300 μΩ-cm.13. The method of claim 11, wherein the barrier material comprises a metal nitride.14. The method of claim 13, wherein the barrier material comprises titanium nitride.15. The method of claim 11, wherein the barrier material is an insulator.16. The method of claim 8, wherein modifying comprises forming a growth-blocking layer on the first surface.17. The method of claim 16, wherein the growth blocking layer is selectively removed after coating the second surface and prior to further deposition.18. The method of claim 8, wherein modifying comprises forming ligands on the first surface and the second surface and subsequently converting the ligands on the first surface into a growth-blocking layer.19. The method of claim 8, wherein modifying comprises forming a sacrificial layer on the first surface.20. The method of claim 19, wherein the sacrificial layer comprises a material susceptible to etching from exposure to the at least two reactant fluids.21. A method of selectively blocking formation of a thin film by an atomic layer deposition (ALD) process on a first surface compared to a second surface comprising:selectively modifying the first surface; and alternatingly contacting the first and second surfaces with vapor-phase reactants to selectively deposit a material over the second surface relative to the first surface in an atomic layer deposition (ALD) process. 22. The method of claim 21, wherein modifying comprises forming a growth-blocking layer over the first surface.23. The method of claim 21, wherein modifying comprises a physical modification.24. The method of claim 21, wherein modifying comprises a chemical modification.25. The method of claim 24, wherein modifying comprises oxidation.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (29)
Conger Darrell R. (Portland OR) Posa John G. (Lake Oswego OR) Wickenden Dennis K. (Lake Oswego OR), Apparatus for depositing material on a substrate.
Huang Richard J. (Milpitas CA) Cheung Robin W. (Cupertino CA) Rakkhit Rajat (Milpitas CA) Lee Raymond T. (Sunnyvale CA), Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC applica.
Alessandra Satta BE; Karen Maex BE; Kai-Erik Elers FI; Ville Antero Saanila FI; Pekka Juha Soininen FI; Suvi P. Haukka FI, Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
Satta, Alessandra; Maex, Karen; Elers, Kai-Erik; Saanila, Ville Antero; Soininen, Pekka Juha; Haukka, Suvi P., Method for bottomless deposition of barrier layers in integrated circuit metallization schemes.
Kang Sang-bom,KRX ; Lim Hyun-seok,KRX ; Chae Yung-sook,KRX ; Jeon In-sang,KRX ; Choi Gil-heyun,KRX, Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor.
Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
Wang Fei ; Lyons Christopher F. ; Nguyen Khanh B. ; Bell Scott A. ; Levinson Harry J. ; Yang Chih Yuh, Method using a thin resist mask for dual damascene stop layer etch.
Stumborg Michael F. ; Santiago Francisco ; Chu Tak Kin ; Boulais Kevin A., Process for making a semiconductor device with barrier film formation using a metal halide and products thereof.
Mee-Young Yoon KR; Sang-In Lee KR; Hyun-Seok Lim KR, Semiconductor device fabrication method using an interface control layer to improve a metal interconnection layer.
Pore, Viljami J.; Haukka, Suvi P.; Blomberg, Tom E.; Tois, Eva E., Methods for depositing nickel films and for making nickel silicide and nickel germanide.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.