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Tri-gate devices and methods of fabrication 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
  • H01L-021/84
출원번호 US-0367263 (2003-02-14)
발명자 / 주소
  • Chau, Robert S.
  • Doyle, Brian S.
  • Kavalieros, Jack
  • Barlage, Douglas
  • Datta, Suman
  • Hareland, Scott A.
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor &
인용정보 피인용 횟수 : 367  인용 특허 : 11

초록 ▼

The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor bod

대표청구항 ▼

1. A method of forming a semiconductor device comprising:forming an oxidation resistant film on a semiconductor body film formed on an insulating substrate; patterning said oxidation resistant film and said semiconductor body film to form an oxidation resistant mask a semiconductor body having a top

이 특허에 인용된 특허 (11)

  1. Ahmed, Shibly S.; Wang, Haihong; Yu, Bin, Double gate semiconductor device having separate gates.
    상세보기
  2. James W. Adkisson ; John A. Bracchitta ; John J. Ellis-Monaghan ; Jerome B. Lasky ; Effendi Leobandung ; Kirk D. Peterson ; Jed H. Rankin, Double planar gated SOI MOSFET structure.
    상세보기
  3. Chenming Hu ; Tsu-Jae King ; Vivek Subramanian ; Leland Chang ; Xuejue Huang ; Yang-Kyu Choi ; Jakub Tadeusz Kedzierski ; Nick Lindert ; Jeffrey Bokor ; Wen-Chin Lee, Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture.
    상세보기
  4. Lin Horng-Chih (Hsinchu TWX) Chen Liang-Po (Hsinchu TWX) Lin Hsiao-Yi (Hualien Hsien TWX) Chang Chun-Yen (Hsinchu TWX), Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration.
    상세보기
  5. Ha Hyoung C. (Kwangmyungsi KRX), Method of fabricating a thin film transistor having vertical channel.
    상세보기
  6. Bin Yu, Method of forming a double gate transistor having an epitaxial silicon/germanium channel region.
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  7. Krivokapic, Zoran; Buynoski, Matthew, Method of making a self-aligned triple gate silicon-on-insulator device.
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  8. Maegawa Shigeto (Itami JPX), Method of making a semiconductor device having a gate all around type of thin film transistor.
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  9. Choi Jong Moon,KRX ; Kim Jong Kwan,KRX, Method of making a thin film transistor.
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  10. Leonard Forbes ; Wendell P. Noble, Methods for dual-gated transistors.
    상세보기
  11. Maszara, Witold P., Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide.
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이 특허를 인용한 특허 (367)

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  47. Lee, Jam-Wem; Lo, Andy, ESD protection for FinFETs.
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  48. Lee, Jam-Wem; Lo, Ching-Hsiung, ESD protection for FinFETs.
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  49. Chung, Tao-Wen; Ke, Po-Yao; Chung, Shine; Hsueh, Fu-Lung, Electrical anti-fuse and related applications.
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  127. Ko, Chih-Hsin; Wann, Clement Hsingjen, Gradient ternary or quaternary multiple-gate transistor.
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  128. Huang, Yu-Lien; Yeh, Mao-Rong; Tsai, Chun Hsiung; Lee, Tsung-Hung; Lin, Da-Wen; Kwok, Tsz-Mei, High surface dopant concentration semiconductor device and method of fabricating.
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  129. Ko, Chih-Hsin; Wann, Clement Hsingjen, High-mobility multiple-gate transistor with improved on-to-off current ratio.
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  152. Lee, Tsung-Lin; Chang, Chang-Yun, Integrated circuit with multi recessed shallow trench isolation.
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  157. Lin, Da-Wen; Chu, Che-Min; Li, Tsung-Hung; Tseng, Chih-Hung; Lin, Yen-Chun; Wu, Chung-Cheng, LDD epitaxy for FinFETs.
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  163. Chen, Yen-Huei, Level shifter.
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  164. Huang, Chih-Hsiang; Lin, Chia-Pin, Lower parasitic capacitance FinFET.
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  169. Huang, Yu-Lien; Tsai, Chun Hsiung; Wu, Chii-Ming; Fang, Ziwei, Mechanisms of doping oxide for forming shallow trench isolation.
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  175. Datta,Suman; Doyle,Brian S.; Chau,Robert S.; Kavalieros,Jack; Zheng,Bo; Hareland,Scott A., Method and apparatus for improving stability of a 6T CMOS SRAM cell.
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  177. Cheng, Ming-Lung; Lin, Da-Wen; Lin, Yen-Chun, Method and apparatus of forming an integrated circuit with a strained channel region.
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  178. Wang, Chien-Hsun; Chang, Chih-Sheng; Lin, Yi-Tang; Shieh, Ming-Feng, Method and device for increasing fin device density for unaligned fins.
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  179. Wang, Chien-Hsun; Chang, Chih-Sheng; Lin, Yi-Tang; Shieh, Ming-Feng, Method and device for increasing fin device density for unaligned fins.
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  180. Wang, Chien-Hsun; Chang, Chih-Sheng; Lin, Yi-Tang; Shieh, Ming-Feng, Method and device for increasing fin device density for unaligned fins.
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  181. Wang, Chien-Hsun; Chang, Chih-Sheng; Lin, Yi-Tang, Method for adjusting fin width in integrated circuitry.
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  182. Cheng, Ming-Lung; Lin, Yen-Chun; Lin, Da-Wen, Method for enhancing channel strain.
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  183. Lin, Hsien-Hsin; Kwok, Tsz-Mei; Su, Chien-Chang, Method for fabricating a FinFET device.
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  184. Lee, Tsung-Lin; Chang, Chih-Hao; Ko, Chih-Hsin; Yuan, Feng; Xu, Jeff J., Method for fabricating a strained structure.
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  186. Lee, Tsung-Lin; Chang, Chih-Hao; Ko, Chih-Hsin; Yuan, Feng; Xu, Jeff J., Method for fabricating a strained structure and structure formed.
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  190. Chang, Chih-Hao; Xu, Jeff J.; Wang, Chien-Hsun; Yeh, Chih Chieh; Chang, Chih-Hsiang, Method for forming high germanium concentration SiGe stressor.
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  191. Wang, Chien-Hsun; Chang, Chih-Sheng; Shieh, Ming-Feng, Method for forming metrology structures from fins in integrated circuitry.
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  192. Su, Chien-Chang; Lin, Hsien-Hsin; Kwok, Tsz-Mei; Chen, Kuan-Yu; Sung, Hsueh-Chang; Pai, Yi-Fang, Method for incorporating impurity element in EPI silicon process.
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  193. Su, Chien-Chang; Lin, Hsien-Hsin; Kwok, Tsz-Mei; Chen, Kuan-Yu; Sung, Hsueh-Chang; Pai, Yi-Fang, Method for incorporating impurity element in EPI silicon process.
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  194. Joshi,Rajiv V.; Williams,Richard Q., Method for making a FET channel.
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  198. Pawlak, Bartlomiej Jan, Method of fabricating FinFET device and structure thereof.
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  200. Chung, Shu-Wei; Yu, Kuo-Feng; Lin, Shyue-Shyh, Method of fabricating a gate stack integration of complementary MOS device.
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  201. Chung, Shu-Wei; Yu, Kuo-Feng; Lin, Shyue-Shyh, Method of fabricating a gate stack integration of complementary MOS device.
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  204. van Dal, Mark, Method of fabricating a semiconductor device having an epitaxy region.
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  209. Chau,Robert S.; Hareland,Scott A.; Brask,Justin K.; Metz,Matthew V., Method of fabricating semiconductor devices with replacement, coaxial gate structure.
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  210. Cheng, Kangguo; Li, Juntao, Method of fabrication of ETSOI CMOS device by sidewall image transfer (SIT).
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  225. Huang, Chih-Hsiang; Lin, Chia-Pin, Method of making lower parasitic capacitance FinFET.
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  226. Perng, Tsu-Hsiu; Yeh, Chih Chieh; Chen, Tzu-Chiang; Ho, Chia-Cheng; Chang, Chih-Sheng, Method of manufacturing a fin-like field effect transistor (FinFET) device.
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