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Flip-chip adaptor package for bare die 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0699537 (2000-10-30)
발명자 / 주소
  • Moden, Walter L.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 10  인용 특허 : 32

초록

A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as mi

대표청구항

1. A method of forming a wire bond style/flip-chip attachment assembly electrically connecting a semiconductor die having a bond pad pattern to a first substrate having a connector pattern arrangement when the semiconductor die is attached to second adaptor substrate having an upper surface and havi

이 특허에 인용된 특허 (32)

  1. Yoneda Yoshihiro (Kawasaki JPX) Ozawa Takashi (Kawasaki JPX), BGA semiconductor device including a plurality of semiconductor chips located on upper and lower surfaces of a first sub.
  2. Mahulikar Deepak ; Hoffman Paul R. ; Braden Jeffrey S., Ball grid array electronic package.
  3. Ikemizu Morihiko,JPX ; Oie Nobuaki,JPX ; Iwasaki Ken,JPX, Electronic device and semiconductor package.
  4. Degani Yinon (Highland Park NJ) Dudderar Thomas D. (Chatham NJ) Han Byung J. (Scotch Plains NJ) Raju Venkataram R. (New Providence NJ), Electronic device package having electronic device boonded, at a localized region thereof, to circuit board.
  5. Eng Kian Teng,SGX ; Chan Min Yu,SGX ; Goh Jing Sua,SGX ; Low Siu Waf,SGX, Flexible pin location integrated circuit package.
  6. Ackermann Karl-Peter (Niederrohrdorf CHX) Berner Gianni (Baden CHX), Highly integrated circuit and method for the production thereof.
  7. Eide Floyd K. (Huntington Beach CA), IC chip package having chip attached to and wire bonded within an overlying substrate.
  8. Shen Ming-Tung (No. 60 ; Lane 328 ; Li-Shan St. Nei-Hu Dist. ; Taipei City TWX), Integrated circuit chip including superimposed upper and lower printed circuit boards.
  9. Lim Thiam B. (Singapore SGX) Saitoh Tadashi (Singapore SGX) Seow Boon Q. (Singapore SGX), Integrated circuit device and method to prevent cracking during surface mount.
  10. Lin Paul T. (Austin TX), Leaded semiconductor device having accessible power supply pad terminals.
  11. Jones Tim (Chandler AZ) Ommen Denise (Phoenix AZ) Baird John (Scottsdale AZ), Low-profile ball-grid array semiconductor package.
  12. Farnworth Warren M. (Nampa ID) Shrock Ed A. (Boise ID) Clifford Scott (Boise ID) King Jerrold L. (Boise ID) Moden Walter (Boise ID), Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer.
  13. Jiang Tongbi ; Schrock Edward, Method for fabricating BGA package using substrate with patterned solder mask open in die attach area.
  14. Conru H. Ward (Essex Junction VT) Irish Gary H. (Jericho VT) Pakulski Francis J. (Shelburne VT) Slattery William J. (Essex Junction VT) Starr Stephen G. (Essex Junction VT) Ward William C. (Burlingto, Method of making a planarized thin film covered wire bonded semiconductor package.
  15. Akram Salman (Boise ID) Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID), Method of producing a single piece package for semiconductor die.
  16. Chia Chok J. ; Variot Patrick, Method of providing electrical connection between an integrated circuit die and a printed circuit board.
  17. Currie Thomas P. (St. Paul MN) Goldberg Norman (Dresher PA), Multichip thin film module.
  18. Lin Paul T. (Austin TX) McShane Michael B. (Austin TX), Overmolded semiconductor device having solder ball and edge lead connective structure.
  19. Ma Abraham C. (Milpitas CA) Hsueh Paul Y. J. (Concord CA), Packaged integrated circuit add-on card.
  20. Okinaga Takayuki (Akishima JPX) Otsuka Kanji (Higashiyamato JPX) Akasaki Hiroshi (Ohme JPX), Pin-grid array semiconductor device.
  21. Oh Sang E. (Seongnam KRX), Printed circuit board having solder ball mounting groove pads and a ball grid array package using such a board.
  22. Matsuura Hidekazu,JPX ; Iwazaki Yoshihide,JPX ; Ohta Naoto,JPX, Process for fabricating a crack resistant resin encapsulated semiconductor chip package.
  23. Kohno Ryuji (Ibaraki JPX) Kitano Makoto (Tsuchiura JPX) Nishimura Asao (Ushiku JPX) Yaguchi Akihiro (Ibaraki JPX) Kawai Sueo (Ibaraki JPX), Semiconductor device.
  24. Tsubosaki Kunihiro,JPX ; Tanimoto Michio,JPX ; Nishi Kunihiko,JPX ; Ichitani Masahiro,JPX ; Koike Shunji,JPX ; Suzuki Kazunari,JPX ; Kimoto Ryosuke,JPX ; Anjoh Ichiro,JPX ; Jin Taisei,JPX ; Iwaya Aki, Semiconductor device.
  25. Sato Mitsutaka (Kawasaki JPX) Kasai Junichi (Kawasaki JPX) Yoshimoto Masanori (Kawasaki JPX) Takeshita Kouichi (Satsuma JPX), Semiconductor device affixed to an upper and a lower leadframe.
  26. Thompson Kenneth R. (Sunrise FL) Banerj Kingshuk (Plantation FL) da Costa Alves Francisco (Boca Raton FL), Semiconductor device with controlled spread polymeric underfill.
  27. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Stackable chip scale semiconductor package with mating contacts on opposed surfaces.
  28. Toh Tuck Fook,SGX ; Leong Chew Weng,SGX ; Yew Chee Kiang,SGX ; Ong Pang Hup,SGX, Thin chip-size integrated circuit package.
  29. Kryzaniwsky Bohdan R. (Hopewell Junction NY), Three-dimensional memory card structure with internal direct chip attachment.
  30. Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.
  31. Lee Kyu Jin,KRX ; Jeong Do Soo,KRX ; Kim Jae June,KRX, Wire bond packages for semiconductor chips and related methods and assemblies.
  32. Higgins ; III Leo M. (Austin TX), Z-axis compliant mechanical IC wiring substrate and method for making the same.

이 특허를 인용한 특허 (10)

  1. Moden,Walter L., Flip-chip adaptor package for bare die.
  2. Moden, Walter L., Grid array packages.
  3. Moden, Walter L., Grid array packages and assemblies including the same.
  4. Miyata, Tadaaki, Light emitting device and manufacturing method thereof.
  5. Moden, Walter L., Methods for providing and using grid array packages.
  6. Nakamura, Atsushi; Nishi, Kunihiko, Semiconductor device having an improved connected arrangement between a semiconductor pellet and base substrate electrodes.
  7. Nakamura, Atsushi; Nishi, Kunihiko, Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof.
  8. Nakamura, Atsushi; Nishi, Kunihiko, Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof.
  9. Corisis, David J.; Brooks, Jerry M.; Moden, Walter L., Stackable ball grid array package.
  10. Moden, Walter L., Stackable semiconductor device assemblies.
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