IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0371932
(2003-02-21)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
7 인용 특허 :
4 |
초록
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A method for forming a heterojunction bipolar transistor includes forming an epitaxial layer, forming a first polysilicon layer, and forming a dielectric layer on the first polysilicon layer. The first polysilicon layer and the dielectric layer include an opening for exposing a portion of the top su
A method for forming a heterojunction bipolar transistor includes forming an epitaxial layer, forming a first polysilicon layer, and forming a dielectric layer on the first polysilicon layer. The first polysilicon layer and the dielectric layer include an opening for exposing a portion of the top surface of the epitaxial layer. Then, a silicon germanium layer is selectively grown in the opening. The silicon germanium layer is grown on the exposed top surface of the epitaxial layer and on the exposed sidewall of the first polysilicon layer. Next, a spacer is formed along the sidewalls of the dielectric layer and the silicon germanium layer. A second polysilicon layer in electrical contact with the silicon germanium layer is then formed. Accordingly, a low resistance connection between the first polysilicon layer forming the extrinsic base region and the silicon germanium layer forming the intrinsic base region of the transistor is formed.
대표청구항
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1. A method for forming a heterojunction bipolar transistor, comprising:forming an epitaxial layer of a first conductivity type on a semiconductor substrate; forming a first polysilicon layer of a second conductivity type directly on the epitaxial layer; forming a first dielectric layer on the first
1. A method for forming a heterojunction bipolar transistor, comprising:forming an epitaxial layer of a first conductivity type on a semiconductor substrate; forming a first polysilicon layer of a second conductivity type directly on the epitaxial layer; forming a first dielectric layer on the first polysilicon layer, wherein the first polysilicon layer and the first dielectric layer include an opening for exposing a portion of the top surface of the epitaxial layer, the opening being formed by masking and etching of the first dielectric layer and the first polysilicon layer; growing selectively a silicon germanium layer in the opening, wherein the silicon germanium layer is grown on the top surface of the epitaxial layer and on the sidewall of the first polysilicon layer exposed by the opening; forming a spacer along the sidewall of the silicon germanium layer and the sidewall of the first dielectric layer in the opening; and forming a second polysilicon layer of the first conductivity type over the opening, wherein the second polysilicon layer overlies the first dielectric layer and the spacer and is in electrical contact with the silicon germanium layer. 2. The method of claim 1, wherein the epitaxial layer forms a collector region of the transistor, the first polysilicon layer forms an extrinsic base region of the transistor, the silicon germanium layer forms an intrinsic base region of the transistor, and the second polysilicon layer forms an emitter region of the transistor.3. The method of claim 2, wherein the silicon germanium layer comprises a polycyrstalline silicon germanium portion formed at the sidewall of the silicon germanium layer abutting the first polysilicon layer and a single-crystalline silicon germanium portion formed above the epitaxial layer.4. The method of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.5. The method of claim 1, wherein forming a first polysilicon layer and forming a first dielectric layer, wherein the first polysilicon layer and the first dielectric layer include an opening for exposing a portion of the top surface of the epitaxial layer, comprise:depositing a polysilicon film on the epitaxial layer; performing ion implantation using dopants of the second conductivity type; depositing a dielectric film on the polysilicon film; and patterning the polysilicon film and the dielectric film to define the opening, thereby forming the first polysilicon layer and the first dielectric layer. 6. The method of claim 1, wherein the first dielectric layer comprises a silicon oxide layer.7. The method of claim 1, wherein the first dielectric layer comprises a TEOS layer.8. The method of claim 1, wherein forming a spacer along the sidewall of the silicon germanium layer comprises:depositing a second dielectric layer over the first dielectric layer and the silicon germanium layer; and anisotropically etching the second dielectric layer to form the spacer along the sidewall of the first dielectric layer and the sidewall of the silicon germanium layer. 9. The method of claim 8, wherein the second dielectric layer comprises a TEOS layer.10. The method of claim 1, wherein forming a second polysilicon layer of the first conductivity type over the opening comprises:depositing a polysilicon film over the first dielectric layer and the opening; performing ion implantation using dopants of the first conductivity type; and patterning the polysilicon film to form the second polysilicon layer over the opening. 11. The method of claim 1, wherein forming a second polysilicon layer of the first conductivity type over the opening comprises:depositing a polysilicon film over the first dielectric layer and the opening and performing in-situ doping of the polysilicon film using dopants of the first conductivity type; and patterning the polysilicon film to form the second polysilicon layer over the opening. 12. The method of claim 1, wherein growing selectively a silicon germanium layer in the opening comprises growing selectively a silicon germanium carbon layer in the opening.13. The method of claim 1, wherein growing selectively a silicon germanium layer comprises growing a silicon germanium layer using an epitaxial process and performing in-situ doping of the silicon germanium layer using dopants of the second conductivity type.14. A method for forming a heterojunction bipolar transistor, comprising:forming a collector region in a semiconductor layer of a first conductivity type on a semiconductor substrate; forming an extrinsic base region in a polysilicon layer of the second conductivity type overlaying the collector region, the polysilicon layer being formed directly on the semiconductor layer; forming a dielectric layer over the extrinsic base region, wherein the dielectric layer and the extrinsic base region include a central aperture exposing a portion of the top surface of the collector region, wherein the center aperture is formed by masking and etching of the polysilicon layer of the second conductivity type and the dielectric layer; forming an intrinsic base region in the central aperture, the intrinsic base region comprising a silicon germanium layer being selectively grown on an exposed top surface of the collector region and an exposed sidewall of the extrinsic base region in the center aperture; forming a spacer in a dielectric material over the intrinsic base region and along the sidewall of the dielectric layer; and forming an emitter region in a polysilicon layer of the first conductivity type, the emitter region overlying the dielectric layer and the spacer and being in electrical contact with the intrinsic base region. 15. The method of claim 14, wherein the first conductivity type is n-type and the second conductivity type is p-type.16. The method of claim 14, wherein the silicon germanium layer comprises a polycyrstalline silicon germanium portion formed at the sidewall of the silicon germanium layer abutting the extrinsic base region and a single-crystalline silicon germanium portion formed above the exposed top surface of the collector region.17. The method of claim 14, wherein the semiconductor layer comprises an epitaxial silicon layer of the first conductivity layer.18. The method of claim 17, wherein forming an extrinsic base region in a polysilicon layer and forming a dielectric layer over the extrinsic base region, wherein the dielectric layer and the extrinsic base region include a central aperture exposing a portion of the top surface of the collector region, comprise:depositing a polysilicon film on the semiconductor layer; performing ion implantation using dopants of the second conductivity type; depositing a dielectric film on the polysilicon film; and patterning the polysilicon film and the dielectric film to define the central aperture, thereby forming the extrinsic base region and the dielectric layer. 19. The method of claim 14, wherein forming a spacer in a dielectric material comprises:depositing a second dielectric layer over the dielectric layer and the silicon germanium layer; and anisotropically etching the second dielectric layer to form the spacer along the sidewall of the first dielectric layer and the sidewall of the silicon germanium layer. 20. The method of claim 14, wherein growing selectively a silicon germanium layer in the opening comprises growing selectively a silicon germanium carbon layer in the opening.21. The method of claim 14, wherein forming an intrinsic base region comprises:growing selectively a silicon germanium layer in the center aperture and performing in-situ doping of the silicon germanium layer using dopants of a second conductivity type, wherein the silicon germanium layer is grown on the top surface of the collector region and on the sidewall of the extrinsic base region exposed by the center aperture. 22. A method for forming a heterojunction bipolar transistor, comprising:forming an epitaxial layer of a first conductivity type on a semiconductor substrate; forming a first dielectric layer on the epitaxial layer, the first dielectric layer including a first opening for exposing a pardon of the top surface of the epitaxial layer; forming a first polysilicon layer of a second conductivity type on the first dielectric layer and the exposed epitaxial layer, the first polysilicon layer forming a step from the first dielectric layer down to the exposed epitaxial layer; forming a second dielectric layer on the first polysilicon layer, wherein the first polysilicon layer and the second dielectric layer include a second opening for exposing a portion of the top surface of the epitaxial layer, the second opening being smaller than the first opening and being formed by masking and etching of the first polysilicon layer and the first dielectric layer; growing selectively a silicon germanium layer in the second opening, wherein the silicon germanium layer is grown on the top surface of the epitaxial layer and on the sidewall of the first polysilicon layer exposed by the second opening; forming a spacer along the sidewall of the silicon germanium layer and the sidewall of the second dielectric layer in the opening; and forming a second polysilicon layer of the first conductivity type over the second opening, wherein the second polysilicon layer overlies the second dielectric layer and the spacer and is in electrical contact with the silicon germanium layer. 23. The method of claim 22, wherein the epitaxial layer forms a collector region of the transistor, the first polysilicon layer forms an extrinsic base region of the transistor, the silicon germanium layer forms an intrinsic base region of the transistor, and the second polysilicon layer forms an emitter region of the transistor.24. The method of claim 23, wherein the silicon germanium layer comprises a polycyrstalline silicon germanium portion formed at the sidewall of the silicon germanium layer abutting the first polysilicon layer and a single-crystalline silicon germanium portion formed above the epitaxial layer.25. The method of claim 22, wherein forming a first polysilicon layer and forming a second dielectric layer, wherein the first polysilicon layer and the second dielectric layer include a second opening for exposing a portion of the top surface of the epitaxial layer, comprise:depositing a polysilicon film on the first dielectric layer and the exposed epitaxial layer; performing ion implantation using dopants of the second conductivity type; depositing a dielectric film on the polysilicon film; and patterning the polysilicon film and the dielectric film to define the second opening, thereby forming the first polysilicon layer and the second dielectric layer. 26. The method of claim 22, wherein the first dielectric layer and the second dielectric layer each comprises a TEOS layer.27. The method of claim 22, wherein forming a spacer along the sidewall of the silicon germanium layer comprises:depositing a third dielectric layer over the second dielectric layer and the silicon germanium layer; and anisotropically etching the third dielectric layer to form the spacer along the sidewall of the second dielectric layer and the sidewall of the silicon germanium layer. 28. The method of claim 22, wherein growing selectively a silicon germanium layer comprises growing a silicon germanium layer using an epitaxial process and performing in-situ doping of the silicon germanium layer using dopants of the second conductivity type.
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