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Flip-chip die and flip-chip package substrate

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/52
출원번호 US-0709265 (2004-04-26)
우선권정보 TW-0205886 (2002-04-29)
발명자 / 주소
  • Hsu, Chi-Hsing
출원인 / 주소
  • VIA Technologies, Inc.
대리인 / 주소
    Jiang Chyun IP Office
인용정보 피인용 횟수 : 61  인용 특허 : 1

초록

A flip-chip die and a flip-chip package substrate. The flip-chip die has an active surface containing a plurality of core power/ground pads, at least one signal pad rings, at least one power pad rings and at least one ground pad rings. The core power/ground pads are located in the central region of

대표청구항

1. A flip-chip package substrate, comprising:a plurality of wiring layers forming a stack and having an uppermost wiring layer, a bottommost layer, and at least one inner wiring layer; a plurality of insulation layers sandwiched between two neighboring wiring layers for isolating the wiring layers s

이 특허에 인용된 특허 (1)

  1. Shuichi Arima JP; Osamu Shimada JP, Wiring board, semiconductor package and semiconductor device.

이 특허를 인용한 특허 (61)

  1. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  2. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
  3. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  4. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  5. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  6. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  7. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  8. Liaw,Yuan Tsang; Hsu,Chi Hsing; Hsu,Hsing Chou, Chip structure with arrangement of side pads.
  9. Cohn,Charles, Flexible circuit substrate for flip-chip-on-flex applications.
  10. Akashi, Tomoko, Flip chip ball grid array package.
  11. Kim, Oh Han; Kim, Kyung Moon, Flip chip interconnection system having solder position control mechanism.
  12. Shiffer,Stephen R., High temperature package flip-chip bonding to ceramic.
  13. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  14. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  15. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  17. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  20. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  21. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  22. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  23. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  24. Chi, HeeJo; Foh, Bartholomew Liao Chung; Alvarez, Sheila Marie L.; Camacho, Zigmund Ramirez; Cuong, Dao Nguyen Phu, Integrated circuit packaging system with insulated trace and method of manufacture thereof.
  25. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  26. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  27. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  28. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  29. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  30. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  31. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  32. Garcia,Jason A., Microelectronic assembly having a perimeter around a MEMS device.
  33. Kimura,Yoshiyuki; Kikuchi,Atsushi; Ikemoto,Yoshihiko, Multilayer board and a semiconductor device.
  34. Kimura,Yoshiyuki; Kikuchi,Atsushi; Ikemoto,Yoshihiko, Multilayer board and a semiconductor device.
  35. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  36. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  37. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  38. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  39. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  40. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  41. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  42. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  43. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  44. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  45. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  46. You, SE-Ho; Lee, Jinho, Semiconductor package.
  47. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  48. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
  49. Hool,Vincent, Techniques for flip chip package migration.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  58. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  59. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  60. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  61. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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