Method for manufacturing multi-kind and small quantity semiconductor products in a mass-production line and system thereof
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0956151
(2001-09-20)
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우선권정보 |
JP-0079704 (1999-03-24) |
발명자
/ 주소 |
- Takagi, Osamu
- Iizuka, Tsuneo
- Honda, Tetsurou
- Honda, Takuya
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출원인 / 주소 |
|
대리인 / 주소 |
Westerman, Hattori, Daniels &
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인용정보 |
피인용 횟수 :
2 인용 특허 :
5 |
초록
▼
A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. One aspect of the present invention, there is provided the method for manufacturing a semiconductor device through a plurality of fabrication processing steps,
A method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof are provided. One aspect of the present invention, there is provided the method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially with a plurality of chips on a wafer based on a chip identification information formed on the wafer, the method comprises at least two steps sharing the chip identification information before at least one of the two steps is carried out, wherein the steps are not immediately neighbored with each other in fabrication processing sequence.
대표청구항
▼
1. A method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially in a fabrication processing sequence with a plurality of chips on a wafer by the corresponding fabrication processing appa
1. A method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially in a fabrication processing sequence with a plurality of chips on a wafer by the corresponding fabrication processing apparatus, the method comprisingat least two steps in the fabrication processing steps sharing at least a part of a chip identification information with a wafer map by distributing the chip identification information to the corresponding fabrication processing apparatus, wherein said at least two steps include steps not adjacent to each other in the fabrication processing sequence. 2. The method according to claim 1, wherein at least one of the steps sharing the chip identification information includes a preparing operation needed to perform the corresponding fabrication processing step, the preparing operation being carried out based on the chip identification information in advance to the corresponding fabrication processing step.3. The method according to claims 1, wherein one of the steps sharing the chip identification information includes adding new processing information resulted from performance of the corresponding processing step to the chip identification information.4. The method according to claims 1, wherein the chip identification information includes a lot number, a wafer number, a chip coordinates or chip property.5. The method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the fabrication processing steps being carried out sequentially with a plurality of chips on a wafer by the corresponding fabrication processing apparatus, the method comprising:at least one of the plurality of fabrication processing steps distributes a chip identification information with a wafer map to at least another of the plurality of fabrication processing steps which is subsequent to but not adjacent to at least one of the plurality of fabrication processing steps, wherein each of the plurality of fabrication processing steps is carried out based on the chip identification information. 6. The method according to claim 5, wherein at least one of the plurality of fabrication processing steps includes a preparing operation needed to perform the corresponding fabrication processing step, the preparing operation being carried out based on the chip identification information in advance to the corresponding fabrication processing step.7. The method according to claims 5, wherein each of the steps sharing the chip identification information includes adding new processing information resulted from performance of the corresponding processing step to the chip identification information.8. The method for manufacturing a semiconductor device through a plurality of fabrication processing steps, each of the plurality of fabrication processing steps being carried out sequentially in a fabrication processing sequence based on a chip identification information with a wafer map the method comprising a step of:sending additional processing information resulted from performance of one of the plurality of fabrication processing steps with the chin identification information to at least another of the plurality of fabrication processing, wherein the fabrication processing steps sharing the additional processing information with each other are not adjacent to each other in the fabrication processing sequence. 9. The method according to claim 8, wherein the chip identification information includes at least one of a lot number, a wafer number or a chip property.10. The method according to claims 8, further comprising the steps of:superposing the additional processing information on the chip identification information formed on a wafer; and subsequently, carrying out at least one of the plurality of fabrication processing steps based on the superposed chip identification information. 11. The method according to claims 8, wherein the chip identification information formed on a wafer is superposed with first and second processing information resulted from performance of first and second processing steps, respectively, and then a third processing step subsequent to the first and second processing steps is carried out based on the superposed chip identification information.12. A method for writing chip identification information on a wafer of integrated semiconductor, the method comprising:a first assigning step of assigning a first digit to a chip which is located in a left-most column of an uppermost row on the wafer; a second assigning step of assigning first subsequent digits to chips which are located from a second left-most column to a right-most column of the uppermost row on the wafer; a third assigning step of assigning a first following digit to a chip which is located in a right-most column of a second uppermost row on the wafer; a fourth assigning step of assigning second subsequent digits to chips which are located from a second right-most column to a left-most column of the second uppermost row on the wafer; a fifth assigning step of assigning a second following digit to a chip which is located in a left-most column of a third uppermost row on the wafer; a sixth assigning step of assigning third subsequent digits to chips which are located from another second left-most column to another right-most column of the third uppermost row on the wafer; a repeating step of repeating from the third assigning step to the sixth assigning step until reaching the chip which is located in the left-most column of the lowermost row or in the right-most column of the lowermost row; and a beam writing step of beam-writing the chip identification information on the chips of the wafer in the order of the assigned digit. 13. The method according to claim 12, wherein the chip identification information includes at least one of a lot number, a wafer number, a chip number, a relative addresses and an additional information.14. The method according to claim 12, wherein the chip identification information is beam-written on one of the chip or an area between chips.15. The method according to claim 12, wherein the additional information includes at least one of history data of each of fabrication processing or testing results.
이 특허에 인용된 특허 (5)
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Oshima Takefumi (Kanagawa JPX), Computer-controlled individual chip management system for processing wafers.
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Guy Dupenloup FR, Method of handling macro components in circuit design synthesis.
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Shiell Jonathan H. ; Chen Ian, Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microi.
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Lofstrom Keith, System for providing an integrated circuit with a unique identification.
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Ginter Karl L. ; Shear Victor H. ; Sibert W. Olin ; Spahn Francis J. ; Van Wie David M., Systems and methods for secure transaction management and electronic rights protection.
이 특허를 인용한 특허 (2)
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Sunaoshi, Hitoshi, Lithography apparatus and lithography method.
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Jensen,John, Method for reducing reticle set cost.
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