초록 ▼

A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal l

A semiconductor device of the present invention has (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad which is provided on the interlayer insulating film, (4) a barrier metal layer which is provided on the active element with the interlayer insulating film therebetween, so that the pad metal is formed on the barrier metal layer, and (5) an insulating layer having high adherence to the barrier metal layer, the insulating layer being provided between the interlayer insulating film and the barrier metal layer. With this arrangement, the adherence between the barrier metal layer, the insulating film and the interlayer insulating film is surely improved, and even in the case where an external force is applied to the electrode pad upon bonding or after bonding, the barrier metal layer hardly comes off the part thereunder. Therefore, the breakdown of a level difference compensating film, and the exfoliation of the barrier metal layer from the interlayer insulating film can be prevented, while the semiconductor device of the area pad structure featuring lower costs, high quality, and high liability is constantly mass-produced. Besides, the yield of the semiconductor device is surely improved.

대표청구항 ▼

1. A semiconductor device, comprising:an active element provided on a semiconductor substrate, said active element including at least two diffusion layers and a gate electrode; a metal wiring layer provided on said active element; an interlayer insulating film covering said active element; a pad met

1. A semiconductor device, comprising:an active element provided on a semiconductor substrate, said active element including at least two diffusion layers and a gate electrode; a metal wiring layer provided on said active element; an interlayer insulating film covering said active element; a pad metal for an electrode pad forming an external electrical terminal for said semiconductor device, said pad metal being provided over said interlayer insulating film and substantially covering the at least two diffusion layers and said gate electrode of the active element, wherein said active element is on a side of the interlayer insulating film opposite to the pad metal and said pad metal is over the active element; and a barrier metal layer provided over said active element and said interlayer insulating film, so that said pad metal is provided on said barrier metal layer and covering said active element, wherein: said interlayer insulating film has at least a level difference compensating film for compensating for a level difference of the metal wiring layer, wherein said level difference compensating film is between portions of the metal wiring layer; and said level difference compensating film under said pad metal is substantially completely removed. 2. The semiconductor device as set forth in claim 1, further comprising a passivation film, said passivation film being formed to cover a large part of said pad metal, and an aperture in said passivation film having an edge adjacent an inside edge of said pad metal.3. The semiconductor device as in claim 2, further comprising another barrier metal layer, said another barrier metal layer is provided on the passivation film and the pad metal which is exposed by a window in the passivation film.4. The semiconductor device as set forth in claim 1, wherein said pad metal is connected to said metal wiring layer via a through-hole in said interlayer insulating film, wherein the through-hole does not penetrate the level difference compensating film.5. A semiconductor device, comprising:an active element provided on a semiconductor substrate, said active element including at least two diffusion layers and a gate electrode; a metal wiring layer provided on said active element; an interlayer insulating film covering said active element; a pad metal for an electrode pad forming an external electrical terminal for said semiconductor device, said pad metal being provided over said interlayer insulating film and substantially covering the at least two diffusion layers and said gate electrode of the active element, wherein said active element is on a side of the interlayer insulating film opposite to the pad metal and said pad metal is over the active element; and a barrier metal layer provided over said active element and said interlayer insulating film, so that said pad metal is provided on said barrier metal layer and covering said active element, wherein:said interlayer insulating film has at least a level difference compensating film for compensating for a level difference of the metal wiring layer, wherein said level difference compensating film under the pad metal is not disposed over a highest portion of the metal wiring layer and said compensating film is disposed between portions of the metal wiring layer; and said level difference compensating film is formed to a minimum thickness necessary for compensating for the level difference of the metal wiring layer. 6. The semiconductor device as set forth in claim 5, wherein said pad metal is connected to said metal wiring layer via a through-hole in said interlayer insulating film, wherein the through-hole does not penetrate the level difference compensating film.7. The semiconductor device as set forth in claim 5 wherein the interlayer insulating film further comprises a first layer and said level difference compensating film is coplanar with a highest portion of the first layer of the interlayer insulating film.8. A semiconductor device, comprising:an active element provided on a semiconductor substrate, said active element including at least two diffusion layers and a gate electrode; a lower interlayer insulating film formed to cover said active element; a metal wiring layer provided on said lower interlayer insulating film; an upper interlayer insulating film having a third layer formed to cover said metal wiring layer; and a pad metal for an electrode pad forming an external electrical terminal for said semiconductor device, said pad metal being provided over said interlayer insulating film and substantially covering the at least two diffusion layers and a gate electrode of the active element, wherein said active element is on a side of the upper and lower interlayer insulating films opposite to the pad metal, and said pad metal is over the active element; another metal wiring layer formed over the active element; wherein each of said lower and upper interlayer insulating films have a trilaminar structure, each of a first layer and the third layer of the trilaminar film being a silicon nitride film or a silicon oxide film, while a second layer of the trilaminar film being formed of spin-on-glass, and the second layer of the upper interlayer insulating film formed to a minimum thickness necessary for compensating the level difference of the another metal wiring layer and wherein said second layer of the upper interlayer insulating film under the pad metal is not disposed over a highest portion of the another metal wiring layer and is disposed between portions of the another metal wiring layer, wherein the second layer is below the third layer of the upper interlayer insulting film. 9. The semiconductor device as set forth in claim 8, whereinsaid another metal wiring layer is connected to the at least two diffusion layers, and also connected, via a through-hole, to said metal wiring layer provided on said lower interlayer insulating film said pad metal is connected to said metal wiring layer via a through-hole made at sad upper interlayer insulating film, and the respective through-holes in said upper and lower interlayer insulating films do not penetrate respective second films of said upper and lower interlayer insulating films. 10. The semiconductor device as set forth in claim 8 wherein the second layer of the upper interlayer insulating film is coplanar with a highest portion of the first layer of said upper interlayer insulating film.11. A semiconductor device, comprising:an active element provided on a semiconductor substrate, said active element including at least two diffusion layers and a gate electrode; a first metal wiring layer formed over the active element; a plurality of other metal wiring layers above said active element; and a plurality of interlayer insulating films each being provided between a pair of said metal wiring layers, wherein said plurality of interlayer insulating films and plurality of metal wiring layers are vertically aligned above the active element; wherein each interlayer insulating film has a multilayer structure including at least a spin-on-glass film sandwiched between insulating films formed of a silicon nitride film or a silicon oxide film; further wherein the film formed of spin-on-glass in the interlayer insulating film is formed to a minimum thickness necessary for compensating for a level difference of one of said metal wiring layers and wherein the spin-on-glass film is between the one of said metal wiring layers and said spin-on-glass film is disposed under the pad metal so as to not cover a highest level of the one of said metal wiring layers; a pad metal for an electrode pad forming an external electrical terminal for said semiconductor device, said pad metal being provided over said interlayer insulating films and over the active element. 12. The semiconductor device as in claim 11 wherein the pad metal substantially covers at least two diffusion layers and said gate electrode of the active element, wherein said active element is on a side of the interlayer insulating film opposite to the pad metal.13. The semiconductor device as set forth in claim 11 whereinsaid first metal wiring layer is connected to the at least two diffusion layers, a pair of upper and lower metal wiring layers of said metal wiring layers are connected to each other via a through-hole, each interlayer insulating film having the through-hole, and the through-hole is formed so as not to penetrate a spin-on-glass of each interlayer insulating film. 14. The semiconductor device as set forth in claim 11 wherein the spin-on-glass film is coplanar with a highest portion of a lower one of said silicon nitride film and said silicon oxide film of the interlayer insulating film.