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Flip clip attach and copper clip attach on MOSFET device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-023/495
출원번호 US-0548946 (2000-04-13)
발명자 / 주소
  • Estacio, Maria Cristina B.
  • Quinones, Maria Clemens Y.
출원인 / 주소
  • Fairchild Semiconductor Corporation
대리인 / 주소
    Townsend and Townsend and Crew LLP
인용정보 피인용 횟수 : 23  인용 특허 : 33

초록

A chip device including a leadframe that includes source and gate connections, a bumped die including solder bumps on a top side that is attached to the leadframe such that the solder bumps contact the source and gate connections, and a copper clip attached to the backside of the bumped die such tha

대표청구항

1. A chip device comprising:a leadframe including source and gate connections; a bumped die having solder bumps including source solder bumps and a gate solder bump source and gate on a frontside, the bumped die being attached to the leadframe such that the solder bumps contact the source and gate c

이 특허에 인용된 특허 (33)

  1. Sean T. Crowley ; Blake A. Gillett ; Philip S. Mauri PH; Ferdinand E. Belmonte PH; Remigio V. Burro, Jr. PH; Victor M. Aquino, Jr. PH, Attaching semiconductor dies to substrates with conductive straps.
  2. Joshi Rajeev (Cupertino CA), Carrier based IC packaging arrangement.
  3. Joshi, Rajeev; Tangpuz, Consuelo N.; Manatad, Romel N., Flip chip in leaded molded package and method of manufacture thereof.
  4. Granada, Honorio T.; Joshi, Rajeev; Tangpuz, Connie, Flip chip substrate design.
  5. Temple Victor A. K. (Clifton Park NY) Watrous Donald L. (Clifton Park NY) Neugebauer Constantine A. (Schenectady NY) Burgess James F. (Schenectady NY) Glascock ; II Homer H. (Scotia NY), Hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip.
  6. Neugebauer Constantine A. (Schenectady NY) Daum Wolfgang (Schenectady NY), High current hermetic package including an internal foil and having a lead extending through the package lid and a packa.
  7. Joshi Rajeev, High performance flip chip package.
  8. Joshi Rajeev, High performance flip chip package.
  9. Joshi, Rajeev, High performance multi-chip flip chip package.
  10. Rajeev Joshi, High performance multi-chip flip chip package.
  11. Joshi, Rajeev, High performance multi-chip flip package.
  12. Izak Bencuya ; Maria Christina B. Estacio PH; Steven P. Sapp ; Consuelo N. Tangpuz PH; Gilmore S. Baje PH; Rey D. Maligro PH, Low Resistance package for semiconductor devices.
  13. Krum Alvin L. (Huntington Beach CA) Conklin Charles W. (Huntington Beach CA), Low resistance electrical interconnection for synchronous rectifiers.
  14. Estacio, Maria Cristina B.; Tumulak, Margie, MOSFET device with multiple gate contacts offset from gate contact area and over source area.
  15. Joshi Rajeev, Method for making a carrier based IC packaging arrangement.
  16. Quinones, Maria Clemens Y.; Baje, Gilmore S.; Estacio, Maria Christina B.; Gestole, Marvin R.; Ledon, Oliver M.; Mepieza, Santos E., Method of packaging a plurality of devices utilizing a plurality of lead frames coupled together by rails.
  17. Joshi, Rajeev, Passivation scheme for bumped wafers.
  18. Estacio, Maria Cristina B.; Madrid, Ruben, Power chip scale package.
  19. Kalfus Martin (Scottsdale AZ) Gooch Robert A. (Mesa AZ), Self-centering electrode for power devices.
  20. Estacio, Maria Cristina B., Semiconductor device including stacked dies mounted on a leadframe.
  21. Joshi, Rajeev; Wu, Chung-Lin, Semiconductor die including conductive columns.
  22. Noquil, Jonathan A.; Estacio, Maria Cristina B., Semiconductor die package including carrier with mask.
  23. Joshi, Rajeev; Sapp, Steven, Semiconductor die package with improved thermal and electrical performance.
  24. Cheah Chuan ; Munoz Jorge ; Kinzer Dan, Semiconductor package.
  25. Eytcheson Charles Tyler, Semiconductor substrate subassembly with alignment and stress relief features.
  26. Ewer Peter R.,GBX, Stress clip design.
  27. Estacio, Maria Cristina B.; Bendal, R. Evan, Supporting gate contacts over source region on MOSFET devices.
  28. Williams Richard K. ; Lam Allen K. ; Choi Alexander K., Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die.
  29. Joshi, Rajeev, Surface mountable optocoupler package.
  30. Joshi Rajeev, Thermally enhanced micro-ball grid array package.
  31. Rajeev Joshi, Unmolded package for a semiconductor device.
  32. Rajeev, Joshi, Unmolded package for a semiconductor device.
  33. Joshi, Rajeev; Tangpuz, Consuelo; Cruz, Erwin Victor R., Wafer-level coated copper stud bumps.

이 특허를 인용한 특허 (23)

  1. Otremba, Ralf, Electronic component having exposed surfaces.
  2. Estacio,Maria Cristina B.; Quinones,Maria Clemens Y., Flip clip attach and copper clip attach on MOSFET device.
  3. Yilmaz, Hamza; Xue, Yan Xun; Lu, Jun; Wilson, Peter; Huo, Yan; Niu, Zhiqiang; Lu, Ming-Chen, Hybrid packaged lead frame based multi-chip semiconductor device with multiple interconnecting structures.
  4. Otremba, Ralf, Interconnection structure, electronic component and method of manufacturing the same.
  5. Cusack, Michael D., Leadframe including die paddle apertures for reducing delamination.
  6. Disney, Donald R.; Shah, Hemal N., Method and system for co-packaging vertical gallium nitride power devices.
  7. Shah, Hemal N.; Disney, Donald R., Method and system for interleaved boost converter with co-packaged gallium nitride power devices.
  8. Lu, Jun; Sun, Ming; Ho, Yueh-Se; Liu, Kai; Shi, Lei, Multi-layer lead frame package and method of fabrication.
  9. Madrid, Ruben P.; Manatad, Romel N., Packaged semiconductor device with dual exposed surfaces and method of manufacturing.
  10. Madrid, Ruben P.; Manatad, Romel N., Packaged semiconductor device with dual exposed surfaces and method of manufacturing.
  11. Cabahug, Elsie Agdon; Gestole, Marvin Rosalejos; Tumulak Rios, Margie Sebial; Montayre, Lilith U.; Manatad, Romel N., Robust leaded molded packages and methods for forming the same.
  12. Cabahug,Elsie Agdon; Gestole,Marvin Rosalejos; Tumulak Rios,Margie Sebial; Montayre,Lilith U.; Manatad,Romel N., Robust leaded molded packages and methods for forming the same.
  13. Otremba, Ralf, Semiconductor component and methods to produce a semiconductor component.
  14. Koenigsberger, Alexander; Schiess, Klaus, Semiconductor device with a semiconductor chip using lead technology and method of manufacturing the same.
  15. Cruz, Erwin Victor R.; Cabahug, Elsie; Shian, Ti Ching; Iyer, Venkat, Semiconductor die package using leadframe and clip and method of manufacturing.
  16. Cruz,Erwin Victor R.; Cabahug,Elsie; Shian,Ti Ching; Iyer,Venkat, Semiconductor die package using leadframe and clip and method of manufacturing.
  17. Madrid, Ruben P., Semiconductor die package with clip interconnection.
  18. St. Germain, Stephen; Arbuthnot, Roger M.; Moens, Peter, Semiconductor package for a lateral device and related methods.
  19. St. Germain, Stephen; Arbuthnot, Roger; Moens, Peter, Semiconductor package for a lateral device and related methods.
  20. Yilmaz, Hamza; Zhang, Xiaotian; Xue, Yan Xun; Bhalla, Anup; Lu, Jun; Liu, Kai; Ho, Yueh-Se; Amato, John, Stacked dual chip package and method of fabrication.
  21. Xue, Yan Xun; Ho, Yueh-Se; Shi, Lei; Lu, Jun; Zhao, Liang, Stacked power semiconductor device using dual lead frame and manufacturing method.
  22. Wu,Chung Lin; Joshi,Rajeev D., Thermal enhanced upper and dual heat sink exposed molded leadless package.
  23. Wu, Chung-Lin; Joshi, Rajeev D., Thermal enhanced upper and dual heat sink exposed molded leadless package and method.
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