초록 ▼

An encoder adds an identifier, being different when the coding should be done or not, into a predetermined location in an original signal, while a decoder reads out the identifier added and detects the condition of coding, so as to decide the execution (ON) of the decoding process to be done or not,

An encoder adds an identifier, being different when the coding should be done or not, into a predetermined location in an original signal, while a decoder reads out the identifier added and detects the condition of coding, so as to decide the execution (ON) of the decoding process to be done or not, automatically. Further, in each of the encoder and the decoder, there is provided a delay output portion, which provides an output treated with only a specific delay but not executing the coding/decoding thereon, separately from a coding process portion or a decoding process portion, wherein a selection can be made, at which one of the signals from the respective process portions and the delay output portion should be outputted, by a setup in an outside operation system with use of a selector.

대표청구항 ▼

1. A decoder for a forward error correcting code, for decoding a digital signals of a frame, being encoded for error correction by a unit of block divided and inserted with an error correction code therein, and transmitted periodically at a time constant period, comprising:an error correction portio

1. A decoder for a forward error correcting code, for decoding a digital signals of a frame, being encoded for error correction by a unit of block divided and inserted with an error correction code therein, and transmitted periodically at a time constant period, comprising:an error correction portion receiving the digital signals of said frame transmitted periodically at the time constant period and conducting error correction upon each of the blocks thereof, said digital signal being encoded for error correction, for providing an output having an error corrected therein; a fixed delay portion receiving said digital signals of the frame being encoded for error correction, for providing an output by delaying said digital signal of the frame being encoded for error correction, for at least a fixed time corresponding to said constant time period of said a sum of a time necessary for receiving one of the blocks and a time necessary for conducting the error correction upon each of the blocks; a through processing portion receiving said digital signals of the frame being encoded for error correction, for providing an output without delaying said digital signals of the frame being encoded for error correction; and a selecting portion, receiving and selecting one of the outputs of said error correcting portion, said fixed delay portion, and said through processing portion, so as to provide an output therefrom. 2. A decoder for a forward error correcting code as defined in claim 1, wherein said digital signal are time division multiplex signals, being disposed in a predetermined transmission frame at a constant time period.3. A decoder for a forward error correcting code as defined in claim 1, wherein said digital signals are transmitted using either one of SDH defined in ITU-T Recommendation and SONET defined in ANSI Standard.4. A decoder for a forward error correcting code as defined in claim 1, wherein said digital signals can be encoded for error correction in accordance with a system coding.5. A decoder for a forward error correcting code as defined in claim 1, wherein said digital signals are encoded for error correction using Hamming code.6. A decoder for a forward error correcting code as defined in claim 1, wherein said digital signals are encoded for error correction using Reed-Solomom code.7. A decoder for a forward error correcting code as defined in claim 1, wherein said digital signals areencoded for error correction using BCH code. 8. A decoder for a forward error correcting code as defined in claim 1, wherein said selecting portion makes selection upon basis of a control signal provided from outside of said decoder.