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A receiver that receives a long pseudonoise (PN) code signal composed of two shorter codes interleaved with one another, includes a correlator unit that correlates the received signal with one or more reference codes corresponding to the two interleaved codes, respectively, and generates correlation

A receiver that receives a long pseudonoise (PN) code signal composed of two shorter codes interleaved with one another, includes a correlator unit that correlates the received signal with one or more reference codes corresponding to the two interleaved codes, respectively, and generates correlation signals. The receiver also includes an even code detector coupled to the correlator unit, for detecting from the correlation signals one of the two shorter codes, and an odd code detector coupled to the correlator unit, for detecting from the correlation signals the short code that is not detected by the even detector. A delay unit is coupled to the even and odd code detectors, and delays the even or the odd correlation signals so as to align the correlation signals. The aligned signals are combined and evaluated by a merit function. If the combined signals exceed a threshold value the short codes are determined to be aligned, the phase of each code can be determined, and the phase of the longer code can be determined from the determined phases of the shorter codes. The receiver can detect two short PN codes that have been combined, such as by interleaving the short codes, to create a long PN code. Hence, the receiver can inexpensively detect the two short codes which allows the receiver to detect the long code with high gain.

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1. A method of detecting from a received signal a long code composed from first and second codes interleaved with each other, wherein the first code has a length of n symbols and the second code has a length of m symbols, the method comprising:a) demultiplexing the received signal into alternating s

1. A method of detecting from a received signal a long code composed from first and second codes interleaved with each other, wherein the first code has a length of n symbols and the second code has a length of m symbols, the method comprising:a) demultiplexing the received signal into alternating symbol streams; b) correlating the first symbol stream with a first reference code to produce a sequence of first correlation signals, and correlating the second symbol stream with a second reference code to produce a sequence of second correlation signals; c) summing the sequence of first correlation signals over a first predetermined length to produce a first correlation sum, and summing the sequence of second correlation signals over a second predetermined length to produce a second correlation sum; and d) processing the first and second correlation sums to produce a signal indicative of the phase of the long code, wherein c) includes c1) adding a current first correlation signal x1 of the sequence of first correlation signals with a rolling sum stored at a current address of a first rolling sum memory thereby generating a first sum, storing the first sum in the first rolling sum memory at the current address, and incrementing the first rolling sum memory=s address modulo n; c2) adding a current second correlation signal x2 of the sequence of second correlation signals with a rolling sum stored at a current address of a second rolling sum memory thereby generating a second sum, storing the second sum in the second rolling sum memory at the current address, and incrementing the second rolling sum memory=s address modulo m; c3) subtracting first and second sum delay values from the first and second sums, respectively, to generate first and second difference signals, wherein the first sum delay value corresponds to the (x1?n)th rolling sum and the second sum delay value corresponds to the (x2?m)th rolling sum; c4) storing the first sum in a first sum delay memory at a current address of the first sum delay memory, and then incrementing the first sum delay memory=s address modulo n·m; and c5) storing the second sum in a second sum delay memory at a current address of the second sum delay memory, and then incrementing the second sum delay memory=s address modulo n·m. 2. The method of claim 1, wherein m and n are mutually prime.3. The method of claim 2, wherein the first predetermined length is n symbols and the second predetermined length is m symbols.4. The method of claim 3, wherein the first and second predetermined lengths are equal to n symbols.5. The method of claim 1, wherein d) includesd1) delaying one of the first and second difference signals by a predetermined delay, and outputting first and second correlation sums; d2) applying a merit function to the first and second correlation sums; d3) determining the phases of the first and second short codes based on the merit function; and d4) detecting the phase of the long code based on the phases of the first and second short codes. 6. The method of claim 1, wherein d) includesd1) applying a merit function to the first and second correlation sums thereby generating first and second merit values; d2) determining the phases of the first and second short codes based the first and second merit values; and d3) detecting the phase of the long code based on the phases of the first and second short codes. 7. The method of claim 5, wherein the merit function comprises taking the product of the squares of the first and second correlation sums.8. The method of claim 5, wherein the merit function comprises taking the minimum of the squares of the first and second correlation sums.9. The method of claim 5, wherein the predetermined delay is one symbol.10. The method of claim 5, wherein in b) the first and second symbol streams are correlated with at least n instances of the first and second reference codes, respectively, each instance being delayed by a predetermined amount; and in d3) the phases of the first and second short codes are determined by identifying the amount of delay of the first and second reference codes that produces the sequence of correlation signals that results in first and second correlation sums that produce a merit function result in d2) that exceeds a threshold value.11. The method of claim 5, further comprising determining a time of transmission of the received signal according to the detected phase of the long code.12. The method of claim 5, comprising determining a range between a transmitter and a receiver that receives the received signal, according to the detected phase of the long code.13. An apparatus receiving a signal having first and second codes interleaved with each other, the apparatus comprising:a correlator unit correlating the received signal with first and second reference codes corresponding to the first and second interleaved codes, respectively, and generating correlation signals; an even code detector coupled to the correlator unit, for detecting from the correlation signals one of the first and second codes, and outputting an even code correlation signal; an odd code detector coupled to the correlator unit, for detecting from the correlation signals one of the first and second codes not detected by the even detector and outputting an odd code correlation signal; and a processing unit for processing the even and odd correlation signals to provide timing information, wherein the processing unit includes a delay unit coupled to the even and odd code detectors, delaying at least one of the even and odd code correlation signals, and outputting a delayed correlation signal and an undelayed correlation signal, and a merit function unit coupled to the delay unit combining the delayed and undelayed correlation signals according to a merit function, and a timing unit coupled to the merit function unit for detecting a phase of the first code and a phase of a second code based on the combined correlation signals meeting a threshold value. 14. The apparatus of claim 13 wherein the length of the first code is n symbols and the length of the second code is m symbols, where m and n are mutually prime.15. The apparatus of claim 14, wherein the second reference code is the same as the first reference code.16. An apparatus receiving a signal having first and second codes interleaved with each other, the apparatus comprising:a correlator unit correlating the received signal with first and second reference codes corresponding to the first and second interleaved codes, respectively, and generating correlation signals; an even code detector coupled to the correlator unit, for detecting from the correlation signals one of the first and second codes, and outputting an even code correlation signal; an odd code detector coupled to the correlator unit, for detecting from the correlation signals one of the first and second codes not detected by the even detector and outputting an odd code correlation signal; and a processing unit for processing the even and odd correlation signals to provide timing information, wherein the processing unit includes a merit function unit coupled to the even and odd code detectors and applying a merit function to the even and odd correlation signals thereby generating even and odd merit values, and a timing unit coupled to the merit function unit for detecting a phase of the first code and a phase of a second code based on the even and odd merit values meeting a threshold value. 17. The apparatus of claim 16, wherein the timing unit determines, based on the detected phases of the even and odd codes, detects the phase of a long code formed from the interleaved first and second codes.18. The apparatus of claim 13, wherein the merit function is the product of the squares of the delayed and undelayed correlation signals.19. The apparatus of claim 13, wherein the merit function unit is the minimum of the squares of the delayed and undelayed correlation signals.20. The apparatus of claim 13, wherein the timing unit determines, based on the combination of the delayed and undelayed correlation signals exceeding a threshold value, the phase of a long code formed from the interleaved first and second codes.21. The apparatus of claim 20, further comprising a ranging unit for determining a range between the receiver and a transmitter of the first and second codes, based on the phase of the long code determined by the timing unit.22. The apparatus of claim 20, wherein the correlator unit comprises at least two groups of correlators, the first group of correlators correlating symbols of the first code with a first reference code and the second group of correlators correlating symbols of the second code with a second reference code.23. The apparatus of claim 13, wherein the even code detector comprises:an even code rolling sum storage unit storing a plurality of rolling sums, and outputting one of the rolling sums; an even code adder unit adding the rolling sum output from the even code rolling sum unit to a correlation signal generated by the correlation unit, and outputting a current even code rolling sum, wherein the even code rolling sum storage unit stores the current even code rolling sum; an even code sum delay storage unit outputting a prior even code rolling sum, and storing the current even code rolling sum; and an even code subtracting unit subtracting the prior even code rolling sum output from the even code sum delay storage unit from the current even code rolling sum, thereby producing an even code correlation sum signal. 24. The apparatus of claim 23, wherein the odd code detector comprises:an odd code rolling sum storage unit storing a plurality of rolling sums, and outputting one of the rolling sums; an odd code adder unit adding the rolling sum output from the odd code rolling sum unit to a correlation signal generated by the correlation unit, and outputting a current odd code rolling sum, wherein the odd code rolling sum storage unit stores the current odd code rolling sum; an odd code sum delay storage unit outputting a prior odd code rolling sum, and storing the current odd code rolling sum; and an odd code subtracting unit subtracting the prior odd code rolling sum output from the odd code sum delay storage unit from the current odd code rolling sum, and thereby producing an odd code correlation sum signal. 25. The apparatus of claim 24, wherein the odd and even rolling sum memories each store n and m rolling sums, respectively, and the odd and even delay memories store a multiple of n and m rolling sums, respectively.26. The apparatus of claim 24, further comprising:a first even counter outputting a first even count to the even rolling sum storage unit and the even sum delay storage unit; a second even counter counting in response to an output of the first even counter and outputting a second even count to the even sum delay storage unit, wherein the even rolling sum storage unit outputs the even rolling sum from a location addressed by the first even count and stores the current rolling sum in the location addressed by the first even count, and the even sum delay storage unit outputs the prior even code rolling sum from a location addressed by the first and second even counters, and stores the current even code rolling sum in a location addressed by the first and second even counters. 27. The apparatus of claim 26, further comprising:a first odd counter outputting a first odd count to the odd rolling sum storage unit and the odd sum delay storage unit; a second odd counter counting in response to an output of the odd counter and outputting a second odd count to the odd sum delay storage unit, wherein the odd rolling sum storage unit outputs the odd rolling sum from a location addressed by the first odd count and stores the current rolling sum in the location addressed by the first odd count, and the odd sum delay storage unit outputs the prior odd code rolling sum from a location addressed by the first and second odd counters, and stores the current odd code rolling sum in a location addressed by the first and second odd counters. 28. The apparatus of claim 27, wherein the first even and the second odd counters are modulo m counters, and the second even and the first odd counters are modulo n counters.29. The apparatus of claim 28, wherein the first even counter is a modulo m counter the first odd counter is a modulo n counter, and the second even and second odd counters both together comprise a modulo p counter and a modulo q counter, where p·q is substantially equal to n and the modulo q counter counts in response to the modulo p counter, wherein the even sum delay memory is addressed based on the first even counter and the modulo q counter, and the odd sum delay memory is addressed based on the first odd counter and the modulo q counter.