초록 ▼

A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access oc

A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

대표청구항 ▼

1. A voice over packet system on a chip comprising:a buffer memory; a system bus coupled to the buffer memory; a plurality of bus arbitrators coupled to the system bus; a plurality of functional modules coupled to the plurality of bus arbitrators, each of the plurality of functional modules has a DM

1. A voice over packet system on a chip comprising:a buffer memory; a system bus coupled to the buffer memory; a plurality of bus arbitrators coupled to the system bus; a plurality of functional modules coupled to the plurality of bus arbitrators, each of the plurality of functional modules has a DMA controller to couple to a bus arbitrator of the plurality of bus arbitrators, the DMA controller to provide direct memory access to the buffer memory; wherein the plurality of functional modules includes one or more signal processors to process data of a plurality of communication channels, the one or more signal processors to directly memory access the buffer memory to read data for processing and to write data after processing, a host port to couple to a packet network and transmit and receive packet payloads with the packet network and to directly memory access the buffer memory to read data from and write data into the buffer memory, and a multichannel serial port to couple to a telephone network and transmit and receive data with the telephone network and to directly memory access the buffer memory to read data from and write data into the buffer memory. 2. The voice over packet system on a chip of claim 1, whereinthe plurality of bus arbitrators negotiate access to the system bus by the plurality of functional modules. 3. The voice over packet system on a chip of claim 1, further comprising:a microcontroller coupled to the system bus.