IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0813454
(2001-03-20)
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발명자
/ 주소 |
- Wagner, Sigurd
- Wagner, Matthias
- Ma, Eugene Y.
- Payne, Adam M.
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출원인 / 주소 |
- Aegis Semiconductor, Inc.
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대리인 / 주소 |
Wilmer Cutler Pickering Hale and Dorr LLP
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인용정보 |
피인용 횟수 :
36 인용 특허 :
13 |
초록
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Materials suitable for fabricating optical monitors include amorphous, polycrystalline and microcrystalline materials. Semitransparent photodetector materials may be based on silicon or silicon and germanium alloys. Conductors for connecting to and contacting the photodetector may be made from vario
Materials suitable for fabricating optical monitors include amorphous, polycrystalline and microcrystalline materials. Semitransparent photodetector materials may be based on silicon or silicon and germanium alloys. Conductors for connecting to and contacting the photodetector may be made from various transparent oxides, including zinc oxide, tin oxide and indium tin oxide. Optical monitor structures based on PIN diodes take advantage of the materials disclosed. Various contact, lineout, substrate and interconnect structures optimize the monitors for integration with various light sources, including vertical cavity surface emitting laser (VCSEL) arrays. Complete integrated structures include a light source, optical monitor and either a package or waveguide into which light is directed.
대표청구항
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1. A semitransparent optical detector comprising:a semitransparent PIN diode having at least one polycrystalline semiconductor layer, wherein the polycrystalline semiconductor is a polycrystalline alloy of silicon and germanium. 2. The detector of claim 1, wherein the polycrystalline alloy is microc
1. A semitransparent optical detector comprising:a semitransparent PIN diode having at least one polycrystalline semiconductor layer, wherein the polycrystalline semiconductor is a polycrystalline alloy of silicon and germanium. 2. The detector of claim 1, wherein the polycrystalline alloy is microcrystalline.3. The detector of claim 1, wherein the PIN diode has another layer of at least one of an amorphous semiconductor and a microcrystalline semiconductor.4. The detector of claim 1, further comprising:a transparent substrate upon which the PIN diode is disposed. 5. The detector of claim 4, further comprising:a transparent conductor disposed on a surface of the PIN diode. 6. A semitransparent optical detector comprising:a PIN diode having amorphous silicon P and N layers; and an intrinsic I layer of an alloy of silicon and germanium. 7. The detector of claim 6 on a transparent substrate.8. The detector of claim 7 wherein the substrate is glass.9. The detector of claim 7 wherein the substrate is a polymer.10. The detector of claim 7 wherein the substrate is silicon which is transparent at a wavelength greater than about 1100 nm.11. The detector of claim 6, wherein the concentration of germanium in the I layer is graded from a relatively low concentration adjacent the P and N layers to a relatively high concentration in the interior of the I layer.12. A semitransparent optical detector comprising:a thin film PIN diode which both detects and is semitransparent to light having a wavelength λ; a first conductor at least partly covering and contacting a first surface of the PIN diode, the first conductor being semitransparent to light having the wavelength λ; a second conductor at least partly covering and contacting a second surface of the PIN diode, the second surface being opposite the first surface and also being semitransparent to light having the wavelength λ; and a passivation layer coveting and enclosing all edges of the PIN diode, defining an aperture exposing at least a portion of the first surface of the PIN diode, and exposing a part of the second semitransparent conductor for contact thereto. 13. The detector of claim 12, the passivation layer having a hole defined therethrough, through which contact is made with the second semitransparent conductor.14. The detector of claim 12, further comprising:a patterned metal layer over the passivation layer, including a first conductor entering the aperture to contact the first semitransparent conductor and a second conductor contacting the second semitransparent conductor. 15. The detector of claim 14, wherein the second conductor contacts the second semitransparent conductor through a hole defined in the passivation layer.16. The detector of claim 12, wherein the passivation layer is silicon nitride.17. The detector of claim 12, wherein the passivation layer is silicon dioxide.18. The detector of claim 12, wherein the first transparent conductor extends partly over the passivation layer, the detector further comprising:a patterned metal layer over the passivation layer, including a first conductor contacting the first transparent conductor without entering the aperture and a second conductor contacting the second transparent conductor. 19. A semitransparent optical detector comprising:a thin film PIN diode; a first transparent conductor at least partly covering and contacting a first surface of the PIN diode; a second transparent conductor at least partly covering and contacting a second surface of the PIN diode; a passivation layer covering and enclosing all edges of the PIN diode, defining an aperture on one surface thereof, and exposing a part of the second transparent conductor for contact thereto, wherein the first transparent conductor extends partly over the passivation layer; and a patterned metal layer over the passivation layer, including a first conductor contacting the first transparent conductor without entering the aperture and a second conductor contacting the second transparent conductor. 20. The detector of claim 19, wherein the second conductor contacts the second transparent conductor through a hole defined in the passivation layer.21. The detector of claims 14 or 19, wherein the thin film PIN diode extends to a contact pad position and the first conductor defines a path on the surface of the PIN diode to the contact pad position.22. The detector of claim 21, wherein a region contacted by at least one of the first and second transparent conductors defines a limited active area less than all of the PIN diode.23. The detector of claims 14 or 19, wherein the PIN diode has tapered edges, a top surface of the PIN diode having a smaller area than a bottom surface thereof.24. A small aperture semitransparent optical detector comprising:a first conductive layer; a PIN diode which is semitransparent to and detects light of wavelength λ; a passivation layer covering and enclosing all edges of the PIN diode and defining an aperture exposing an upper surface of the PIN diode, wherein the first conductive layer extends partially under the PIN diode and electrically contacts a bottom surface of the PIN diode leaving unobstructed a portion of the bottom surface directly opposite the aperture so that light can pass through the aperture into the diode and out of the bottom surface without being obstructed by the first conductive layer; and a second conductive layer contacting the surface of the PIN diode through the aperture. 25. The detector of claim 24, wherein the second conductive layer covers the aperture and is a transparent to light of wavelength λ, the detector further comprising:a third conductive layer contacting the second conductive layer outside the aperture. 26. The detector of claim 24, wherein the first conductive layer extends under the PIN diode on only one side and the second conductive layer contacts the exposed surface of the PIN diode in an area that is generally diagonally opposite where the first conductive layer extends under the PIN diode.27. The detector of claim 24, wherein the first side of the PIN diode is one of the p-doped side and the n-doped side of the PIN diode and the exposed surface is of the other of the p-doped side and the n-doped side of the PIN diode.28. The detector of claim 24, further comprising a substrate onto which the first conductive layer is formed, wherein the substrate is transparent to light of wavelength λ, the first conductive layer defines an open area which exposes the underlying substrate, and the PIN diode is formed on the substrate in the open area and partially extending onto the first conductive layer.
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