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Semiconductor device and method of manufacturing the same

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-029/94
  • H01L-031/062
  • H01L-031/113
  • H01L-031/119
출원번호 US-0188103 (2002-07-03)
우선권정보 JP-0135430 (1993-05-12); JP-0345126 (1993-12-20)
발명자 / 주소
  • Maeda, Shigenobu
  • Yamaguchi, Yasuo
  • Kuriyama, Hirotada
  • Maegawa, Shigeto
출원인 / 주소
  • Renesas Technology Corp.
대리인 / 주소
    McDermott Will &
인용정보 피인용 횟수 : 37  인용 특허 : 16

초록

A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second in

대표청구항

1. A semiconductor device in which flow of a number of carriers is controlled by a voltage applied to a gate, comprising:a substrate having a main surface; a first conductive layer of a first conductivity type provided in the main surface of said substrate; to be a first portion of one of source/dra

이 특허에 인용된 특허 (16)

  1. Jastrzebski Lubomir L. (Plainsboro NJ) Ipri Alfred C. (Princeton NJ), CMOS Structure incorporating vertical IGFETS.
  2. Kohyama Yusuke (Kawasaki JPX), Dynamic memory cell using hollow post shape channel thin-film transistor.
  3. Fitch Jon T. (Austin TX) Mazur Carlos A. (Hopewell Junction NY) Witek Keith E. (Austin TX), Dynamic memory device having a vertical transistor.
  4. Tseng Horng-Huei,TWX, Method for fabricating narrow channel field effect transistors having titanium shallow junctions.
  5. Fitch Jon T. (Austin TX) Mazur Carlos A. (Austin TX) Witek Keith E. (Austin TX) Hayden James D. (Austin TX), Method for forming vertical transistor structures having bipolar and MOS devices.
  6. Sivan Richard D. (Austin TX), Method for making a self-aligned vertical thin-film transistor in a semiconductor device.
  7. Fitch Jon T. (Austin TX) Mazur Carlos A. (Austin TX) Witek Keith E. (Austin TX), Method of formation of transistor and logic gates.
  8. Jun Young-Kwon (Seoul KRX), Method of forming a contact hole for a metal line in a semiconductor device.
  9. Manning Monte (Boise ID), Method of forming a thin film transistor.
  10. Gardner Mark I. ; Hause Fred N. ; Fulford ; Jr. H. Jim, Method of reducing MOS transistor gate beyond photolithographically patterned dimension.
  11. Koh Chao-Ming (Hsin-chu TWX), Method to ensure isolation between source-drain and gate electrode using self aligned silicidation.
  12. Maeda Shigenobu,JPX ; Yamaguchi Yasuo,JPX ; Kuriyama Hirotada,JPX ; Maegawa Shigeto,JPX, Semiconductor device having a vertical surround gate metal-oxide semiconductor field effect transistor, and manufactur.
  13. Kumagai Jumpei (Yokohama JPX) Sawada Shizuo (Yokohama JPX), Semiconductor memory device having a bit line constituted by a semiconductor layer.
  14. Sundaresan Ravishankar (Garland TX), Stacked CMOS sRAM with vertical transistors and cross-coupled capacitors.
  15. Ishijima Toshiyuki (Tokyo JPX), Structure of complementary field effect transistor.
  16. Nakata Yoshiro (Ikoma JPX) Matsuo Naoto (Ibaraki JPX) Yabu Toshiki (Hirakata JPX) Matsumoto Susumu (Hirakata JPX) Okada Shozo (Kobe JPX), Thin-film semiconductor device and method of fabricating the same.

이 특허를 인용한 특허 (37)

  1. Juengling, Werner, DRAM cells with vertical transistors.
  2. Juengling,Werner, DRAM cells with vertical transistors.
  3. Abbott, Todd R., DRAM including a vertical surround gate transistor.
  4. Abbott, Todd R., DRAM including a vertical surround gate transistor.
  5. Juengling, Werner, Integrated circuits and transistor design therefor.
  6. Forbes, Leonard, Memory array and memory device.
  7. Forbes, Leonard, Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines.
  8. Forbes, Leonard, Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines.
  9. Forbes, Leonard, Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines.
  10. Masuoka, Fujio; Harada, Nozomu, Method for producing an SGT-including semiconductor device.
  11. Masuoka, Fujio; Harada, Nozomu, Method for producing an SGT-including semiconductor device.
  12. Forbes, Leonard, Method of making a memory array with surrounding gate access transistors and capacitors with global staggered local bit lines.
  13. Gordon, Haller A.; Sanh, Tang D.; Steven, Cummings, Methods of fabricating a memory device.
  14. Haller, Gordon; Tang, Sanh D.; Cummings, Steve, Methods of fabricating a memory device.
  15. Haller, Gordon; Tang, Sanh Dang; Cummings, Steve, Methods of fabricating a memory device.
  16. Juengling, Werner; Lane, Richard, Methods of forming an integrated circuit with self-aligned trench formation.
  17. Lin, Shian-Jyh, Raised vertical channel transistor device.
  18. Tran,Luan, Selective polysilicon stud growth.
  19. Tran,Luan, Selective polysilicon stud growth.
  20. Tran,Luan, Selective polysilicon stud growth.
  21. Tran,Luan, Selective polysilicon stud growth.
  22. Juengling, Werner; Lane, Richard, Self-aligned semiconductor trench structures.
  23. Werner, Juengling; Lane, Richard, Self-aligned semiconductor trench structures.
  24. Juengling, Werner; Lane, Richard, Self-aligned trench formation.
  25. Kato, Kiyoshi; Nagatsuka, Shuhei; Inoue, Hiroki; Matsuzaki, Takanori, Semiconductor device.
  26. Kim, Myung-Ok, Semiconductor device and method of fabricating the same.
  27. Kato, Kiyoshi; Nagatsuka, Shuhei; Inoue, Hiroki; Matsuzaki, Takanori, Semiconductor device having transistor and capacitor.
  28. Haller, Gordon; Tang, Sanh Dang; Cummings, Steve, Semiconductor memory device.
  29. Yamazaki,Shunpei; Miyanaga,Akiharu; Koyama,Jun; Fukunaga,Takeshi, Static random access memory using thin film transistors.
  30. Forbes, Leonard, Surround gate access transistors with grown ultra-thin bodies.
  31. Forbes, Leonard, Surround gate access transistors with grown ultra-thin bodies.
  32. Forbes, Leonard, Surround gate access transistors with grown ultra-thin bodies.
  33. Forbes, Leonard, Surround gate access transistors with grown ultra-thin bodies.
  34. Masuoka, Fujio; Kudo, Tomohiko, Surrounding gate transistor semiconductor device.
  35. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Thin film semiconductor device and its manufacturing method.
  36. Juengling, Werner, Vertical transistors.
  37. Juengling, Werner, Vertical transistors.
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