Method and apparatus for extending the size of a transistor beyond one integrated circuit
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-017/687
출원번호
US-0441790
(2003-05-16)
발명자
/ 주소
Balakrishnan, Balu
출원인 / 주소
Power Integrations, Inc.
대리인 / 주소
Blakely Sokoloff Taylor &
인용정보
피인용 횟수 :
7인용 특허 :
13
초록▼
A technique for extending the size of a power transistor beyond one integrated circuit. In one embodiment, a method of extending the size of a power transistor beyond one integrated circuit includes a master integrated circuit comprising a master control circuit, master driver circuit and master sem
A technique for extending the size of a power transistor beyond one integrated circuit. In one embodiment, a method of extending the size of a power transistor beyond one integrated circuit includes a master integrated circuit comprising a master control circuit, master driver circuit and master semiconductor switch and one or more slave integrated circuits comprising a slave semiconductor switch and a slave driver circuit. In one embodiment the master semiconductor switch terminals are coupled to the corresponding slave semiconductor switch terminals. In one embodiment the master driver circuit input and slave driver circuit inputs are coupled to be driven by a control signal being the output of the master control circuit.
대표청구항▼
1. An apparatus, comprising:a first power transistor on a first integrated circuit chip, the first power transistor having two output terminals and a control terminal; a first driver circuit on the first integrated circuit chip, the first driver circuit having a first driver circuit input and a firs
1. An apparatus, comprising:a first power transistor on a first integrated circuit chip, the first power transistor having two output terminals and a control terminal; a first driver circuit on the first integrated circuit chip, the first driver circuit having a first driver circuit input and a first driver circuit output; a second power transistor on a second integrated circuit chip, the second power transistor having two output terminals and a control terminal; and a second driver circuit on the second integrated circuit chip, the second driver circuit having a second driver circuit input and a second driver circuit output, the two output terminals of the first power transistor coupled to the two output terminals, respectively, of the second power transistor, the first and second driver circuit inputs all coupled to receive a single control signal, the first driver circuit output coupled to drive the control terminal of the first power transistor to switch the first power transistor with the single control signal and the second driver circuit output coupled to drive the control terminal of the second power transistor to switch the second power transistor with the single control signal. 2. The apparatus of claim 1 wherein the first and second driver circuits are all coupled to be powered by a single power source.3. The apparatus of claim 1 wherein the first and second power transistors comprise field effect transistors (FETs).4. The apparatus of claim 3 wherein the first and second power transistors comprise metal oxide semiconductor field effect transistors (MOSFETs).5. The apparatus of claim 1 wherein the first and second power transistors comprise bipolar transistors.6. The apparatus of claim 1 wherein the single control signal is an output of a control circuit included on the first integrated circuit chip.7. The apparatus of claim 6 wherein the control circuit comprises a current sense circuit coupled to the first power transistor to sense a current through the first power transistor, the control circuit coupled to control the current through the first power transistor and a current through the second power transistor with the single control signal.8. The apparatus of claim 6 wherein the control circuit comprises a temperature sense circuit coupled to the first power transistor to sense a temperature of the first power transistor, the control circuit coupled to control power dissipation in the first and second power transistors with the single control signal.9. The apparatus of claim 6 wherein the control circuit comprises a switched mode regulator circuit.10. The apparatus of claim 6 wherein the control circuit comprises a power factor controller circuit.11. The apparatus of claim 6 wherein the control circuit comprises an amplifier circuit.12. The apparatus of claim 1 wherein the apparatus is included in a switched mode power supply.13. The apparatus of claim 1 wherein the apparatus is included in an alternating current (AC) to direct current (DC) power supply.14. The apparatus of claim 1 wherein the apparatus is included in a direct current (DC) to DC power supply.15. The apparatus of claim 1 wherein the apparatus is included in a power factor correction circuit.16. The apparatus of claim 1 wherein the apparatus is included in a power amplifier circuit.17. An apparatus, comprising:a master integrated circuit chip including a master semiconductor switch having two master switch terminals and a master control terminal, the master integrated circuit chip further including a master driver circuit having a master driver output and a master driver input, the master integrated circuit chip further including a master control circuit coupled to output a master control signal; and at least one slave integrated circuit chip including a slave semiconductor switch having two slave switch terminals and a slave control terminal, the at least one slave integrated circuit chip further including a slave driver circuit having a slave driver output and a slave driver input, the two master switch terminals of the master integrated circuit chip coupled to the two slave switch terminals of the at least one slave integrated circuit chip, the master driver input of the master integrated circuit chip and the slave driver input of the at least one slave integrated circuit chip coupled to recieve the master control signal, the master driver output coupled to drive the master control terminal of the master semiconductor switch to switch the master semiconductor switch with the master control signal, the slave driver output coupled to drive the slave control terminal of the slave semiconductor switch to switch the slave semiconductor switch with the master control signal. 18. The apparatus of claim 17 wherein the master and the slave driver circuits are all coupled to be powered by a single power source.19. The apparatus of claim 17 wherein the master and the slave semiconductor switches comprise field effect transistors (FETs).20. The apparatus of claim 19 wherein the master and the slave semiconductor switches comprise metal oxide semiconductor field effect transistors (MOSFETs).21. The apparatus of claim 17 wherein the master control circuit comprises a current sense circuit coupled to the master semiconductor switch to sense a current through the master semiconductor switch.22. The apparatus of claim 21 wherein the current sense circuit is coupled to cause the master control circuit to turn off the master and slave semiconductor switches with the master control signal when the current through the master semiconductor switch exceeds a current limit threshold.23. The apparatus of claim 21 wherein the current circuit is coupled to the two master switch terminals.24. The apparatus of claim 21 wherein the current sense circuit is coupled to detect a voltage drop across an on-resistance of the master semiconductor switch.25. The apparatus of claim 17 wherein the master control circuit comprises a temperature sense circuit thermally coupled to the master semiconductor switch to sense a temperature of the master semiconductor switch, the temperature sense circuit coupled to cause the master control circuit to control power dissipation of the master and slave semiconductor switches with the master control signal.26. The apparatus of claim 17 wherein the master control circuit comprises a switched mode regulator circuit.27. The apparatus of claim 17 wherein the master control circuit comprises a power factor controller circuit.28. The apparatus of claim 17 wherein the master control circuit comprises a digital amplifier circuit.29. The apparatus of claim 17 wherein the apparatus is included in a switched mode power supply.30. The apparatus of claim 17 wherein the apparatus is included in an alternating current (AC) to direct current (DC) power supply.31. The apparatus of claim 17 wherein the apparatus is included in a direct current (DC) to DC power supply.32. The apparatus of claim 17 wherein the apparatus is included in a power factor correction circuit.33. The apparatus of claim 17 wherein the apparatus is included in a digital power amplifier circuit.34. A method, comprising:generating a control signal to switch a first power transistor and a second power transistor; receiving the control signal with a first driver circuit included in a first integrated circuit chip to generate a first drive signal from the control signal; driving the first power transistor included in the first integrated circuit chip with the first drive signal to switch the first power transistor with the control signal; receiving the control signal with a second driver circuit included in a second integrated circuit chip to generate a second drive signal from the control signal; and driving the second power transistor included in the second integrated circuit chip with the second drive signal to switch the second power transistor with the control signal. 35. The method of claim 34 wherein corresponding output terminals of the first and second power transistors are coupled together.36. The method of claim 35 wherein the first and second power transistors are coupled to a single power source.37. The method of claim 34 further comprising correcting a power factor of a circuit.38. The method of claim 34 wherein generating the control signal to switch the first power transistor and the second power transistor further comprises generating the control signal with a control circuit included in the first integrated circuit chip.39. The method of claim 38 further comprising sensing a current through the first power transistor, wherein the control signal is responsive to the current through the first power transistor.40. The method of claim 38 further comprising sensing a temperature of the first power transistor, wherein the control signal is responsive to the temperature of the first power transistor.41. A method, comprising:generating a control signal to switch a master power transistor and at least one slave power transistor; receiving the control signal with a master driver circuit included in a master integrated circuit chip to generate a master drive signal from the control signal; driving the master power transistor included in the master integrated circuit chip with the master drive signal to switch the master power transistor with the control signal; signal with at least one slave driver circuit included in at least one slave integrated circuit chip to generate at least one slave drive signal from the control signal; and driving the at least one slave power transistor included in the at least one slave integrated circuit chip with the at least one slave drive signal to switch the at least one slave power transistor with the control signal. 42. The method of claim 41 wherein corresponding output terminals of the master and the at least one slave power transistors are coupled together.43. The method of claim 41 wherein generating the control signal to switch the master power transistor and the at least one slave power transistor further comprises generating the control signal with a control circuit included in the master integrated circuit chip.44. The method of claim 43 further comprising sensing a current through the master power transistor, wherein the control signal is responsive to the current through the master power transistor.45. The method of claim 43 further comprising sensing a temperature of the master power transistor, wherein the control signal is responsive to the temperature of the master power transistor.
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