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Method for apparatus for polishing outer peripheral chamfered part of wafer

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B24B-001/00
출원번호 US-0959315 (2001-02-21)
우선권정보 JP-0045777 (2000-02-23)
국제출원번호 PCT/JP01/01266 (2002-01-25)
§371/§102 date 20020125 (20020125)
국제공개번호 WO01/62436 (2001-08-30)
발명자 / 주소
  • Mizushima, Kazutoshi
  • Miura, Nakaji
  • Sekine, Yasuhiro
  • Suzuki, Makoto
  • Tomii, Kazuya
출원인 / 주소
  • Shin-Etsu Handotai Co., Ltd.
대리인 / 주소
    Crowell &
인용정보 피인용 횟수 : 77  인용 특허 : 5

초록

In a process for polishing the chamfered peripheral part of a wafer using a polishing cloth while supplying a polishing slurry in order to improve productivity of the process by reducing a polishing time, at least two steps of polishing processes are performed in sequence. The process comprises a fi

대표청구항

1. A method for polishing the chamfered peripheral part of a wafer with a polishing cloth while supplying a polishing slurry comprising the steps of performing a plurality of processes in sequence, wherein the plurality of processes includes at least two polishing processes performed on at least a f

이 특허에 인용된 특허 (5)

  1. Hasegawa Fumihiko (Urawa JPX) Ohtani Tatsuo (Fukushima JPX) Kawano Hiroshi (Fukushima JPX) Yamada Masayuki (Shirakawa JPX), Method and an apparatus for polishing wafer chamfers.
  2. Hasegawa Fumihiko,JPX ; Ohtani Tatsuo,JPX ; Kuroda Yasuyoshi,JPX ; Ichikawa Koichiro,JPX ; Inada Yasuo,JPX, Method for mirror-polishing chamfered portion of wafer and mirror-polishing apparatus.
  3. Krishna Vepa (St. Charles MO) Wisnieski Michael S. (O\Fallon MO) Illig Lois (Troy MO), Method of rough polishing semiconductor wafers to reduce surface roughness.
  4. Steere ; Jr. Robert E. ; Steere ; III Robert E., Wafer notch polishing machine and method of polishing an orientation notch in a wafer.
  5. Hasegawa Fumihiko,JPX ; Kuroda Yasuyoshi,JPX ; Yamada Masayuki,JPX, Wafer processing method and equipment therefor.

이 특허를 인용한 특허 (77)

  1. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  3. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  4. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  5. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  6. Nakayama, Masahiro; Irikura, Masato, Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer.
  7. Nakayama, Masahiro; Irikura, Masato, Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer.
  8. Nakayama, Masahiro; Irikura, Masato, Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer.
  9. Nakayama, Masahiro; Irikura, Masato, Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer.
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  22. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
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  24. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  25. Datta,Suman; Brask,Justin K.; Kavalieros,Jack; Doyle,Brian S.; Dewey,Gilbert; Doczy,Mark L.; Chau,Robert S., Lateral undercut of metal gate in SOI device.
  26. Schwandner, Juergen, Method for chemically grinding a semiconductor wafer on both sides.
  27. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  28. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  29. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  30. Schwandner, Juergen, Method for polishing the edge of a semiconductor wafer.
  31. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  32. Brask,Justin K.; Doyle,Brian S.; Kavalleros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Method of forming a metal oxide dielectric.
  33. Brask, Justin K.; Doyle, Brian S.; Kavalieros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material.
  34. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  35. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  36. Lemaire, Cédric; Batherosse, Romain, Method of shaping an ophthalmic lens.
  37. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  38. Zhang,Yuegang; Doyle,Brian S.; Bourianoff,George I., Multi-gate carbon nano-tube transistors.
  39. Watanabe, Kazutoshi; Yoshida, Takehiro, Nitride semiconductor substrate and method of fabricating the same.
  40. Doyle, Brian S.; Datta, Suman; Jin, Been Yih; Chau, Robert, Non-planar MOS structure with a strained channel region.
  41. Doyle,Brian S.; Datta,Suman; Jin,Been Yih; Chau,Robert, Non-planar MOS structure with a strained channel region.
  42. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
  43. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
  44. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  45. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  46. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  50. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  51. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  54. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
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  73. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
  74. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  75. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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