Method of fabrication of an infrared radiation detector and infrared detector device
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01R-031/26
H01L-021/66
출원번호
US-0861334
(2001-05-18)
우선권정보
EP-0870044 (1997-03-28)
발명자
/ 주소
Fiorini, Paolo
Sedky, Sherif
Caymax, Matty
Baert, Christiaan
출원인 / 주소
Interuniversitair Micro-Elektronica Centrum (IMEC,vzw)
대리인 / 주소
McDonnell Boehnen Hulbert &
인용정보
피인용 횟수 :
5인용 특허 :
24
초록▼
A method of fabricating an infrared detector, a method of controlling the stress in a polycrystalline SiGE layer and an infrared detector device is disclosed. The method of fabricating includes the steps of forming a sacrificial layer on a substrate; patterning said sacrificial layer; establishing a
A method of fabricating an infrared detector, a method of controlling the stress in a polycrystalline SiGE layer and an infrared detector device is disclosed. The method of fabricating includes the steps of forming a sacrificial layer on a substrate; patterning said sacrificial layer; establishing a layer consisting essentially of polycrystalline SiGe on said sacrificial layer; depositing an infrared absorber on said polycrystalline SiGe layer; and thereafter removing the sacrificial layer. The method of controlling the stress in a polycrystalline SiGe layer deposited on a substrate is based on varying the deposition pressure. The infrared detector device comprises an active area and an infrared absorber, wherein the active area comprises a polycrystalline SiGe layer, and is suspended above a substrate.
대표청구항▼
1. A method of fabricating an electrical device comprising:depositing a sacrificial layer comprising a first material on a substrate; depositing a second material on the substrate; contemporaneously forming an active layer portion and at least one connector portion from the second material, wherein
1. A method of fabricating an electrical device comprising:depositing a sacrificial layer comprising a first material on a substrate; depositing a second material on the substrate; contemporaneously forming an active layer portion and at least one connector portion from the second material, wherein the connector electrically couples the active layer portion with circuitry included on the substrate; and removing at least a portion of the sacrificial layer. 2. The method of claim 1, wherein depositing a sacrificial layer includes forming a sacrificial layer on the substrate and patterning the sacrificial layer.3. The method of claim 1, wherein the second material consists essentially of a single material.4. The method of claim 3, wherein the single material comprises polycrystalline silicon.5. The method of claim 3, wherein the single material comprises silicon-germanium.6. The method of claim 3, wherein forming the active layer portion and the at least one connector portion comprises:patterning the second material, so as to contemporaneously form the active area portion, the at least one connector portion and at least one support of the active layer. 7. The method of claim 6, wherein forming the active layer portion and the at least one connector portion further comprises:doping the active layer portion and the at least one connector portion after pattering the second material. 8. A method of fabricating an electrical device comprising:depositing a sacrificial layer on a substrate; forming an active area; forming at least one connector, the connector electrically contacting the active area with circuitry included on the substrate; and removing at least a portion of the sacrificial layer, wherein the active area and the connector consist essentially of a single material, and the active area is suspended above the substrate using one or more supports Conned with the active area. 9. The method of claim 8, wherein forming the active area and forming the at least one connector is performed substantially simultaneously.10. The method of claim 9, wherein forming the active area and forming the at least one connector comprises:patterning the active area and the at least one connector. 11. The method of claim 10, wherein forming the active area and forming the at least one connector further comprises:doping the active area and the at least one connector. 12. The method of claim 9, further comprising:doping the electrical device after forming. 13. The method of claim 12, wherein doping includes performing doping of the at least one connector with a different doping concentration than the active area.14. The method of claim 13, wherein doping the at least one connector includes highly doping the at least one connector.15. The method of claim 12, wherein doping includes performing doping of the active area and the at least one connector.16. The method of claim 11, wherein doping of the active area and the at least one connector includes moderately doping the active area and the at least one connector.17. The method of claim 8, wherein the electrical device comprises an infrared device.18. The method of claim 8, wherein the electrical device comprises a detector.19. The method of claim 8, wherein the single material comprises polycrystalline.20. The method of claim 8, wherein the single material comprises silicon-germanium.21. The method of claim 8, wherein removing includes removing substantially all of the sacrificial layer.22. The method of claim 8, wherein depositing the sacrificial layer comprises:forming a sacrificial layer on the substrate; and patterning the sacrificial layer. 23. The method of claim 8, wherein the active area comprises a material made of polycrystalline Si70%Ge30%.24. The method of claim 23, wherein the active area is deposited by chemical vapor deposition.25. The method of claim 23, wherein the active area is deposited at or below atmospheric pressure.
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이 특허에 인용된 특허 (24)
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