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Method of making a lead-free integrated circuit package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-003/34
출원번호 US-0817330 (2001-03-26)
발명자 / 주소
  • Celaya, Phillip C.
  • Donley, James S.
  • St. Germain, Stephen C.
출원인 / 주소
  • Semiconductor Components Industries, L.L.C.
인용정보 피인용 횟수 : 22  인용 특허 : 7

초록

An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends

대표청구항

1. A method of making an integrated circuit, comprising the step of plating a conductive material to project outwardly from a second surface of a substrate to form a lead-free first lead of the integrated circuit, wherein the lead-free first lead projects outwardly a distance from the second surface

이 특허에 인용된 특허 (7)

  1. Mahulikar Deepak ; Hoffman Paul R. ; Braden Jeffrey S., Ball grid array electronic package.
  2. Celaya Phillip C. ; Kerr John R., Electronic component assembly having an encapsulation material and method of forming the same.
  3. Yano Keiichi,JPX ; Asai Hironori,JPX, Heat transfer configuration for a semiconductor device.
  4. Pryor Michael J. (Woodbridge CT) Singhdeo Narendra N. (New Haven CT) Mahulikar Deepak (Meriden CT), Hermetically sealed package.
  5. Kim Jin-Sung,KRX, Method for fabricating a surface mounting type semiconductor chip package.
  6. Carney Francis J. ; Carson George Amos ; Celaya Phillip C. ; Fuerhaupter Harry ; Jones Frank Tim ; Klosterman Donald H. ; Melton Cynthia M. ; Knapp James Howard ; Nelson Keith E., Microelectronic package including a polymer encapsulated die, and method for forming same.
  7. Mahulikar Deepak (Meriden CT), Process for manufacturing a metal pin grid array package.

이 특허를 인용한 특허 (22)

  1. Stuber, Michael A.; Molin, Stuart B., Back-to-back stacked integrated circuit assembly.
  2. Stuber, Michael A.; Molin, Stuart B., Back-to-back stacked integrated circuit assembly and method of making.
  3. Harun,Fuaida; Koh,Liang Jen; Tan,Lan Chu, Bonding pad for a packaged integrated circuit.
  4. Vasishta,Ronnie; Mihelcic,Stan, Embedded redistribution interposer for footprint compatible chip package conversion.
  5. Stuber, Michael A.; Molin, Stuart B.; Drucker, Mark; Fowler, Peter, Integrated circuit assembly and method of making.
  6. Stuber, Michael A.; Molin, Stuart B.; Drucker, Mark; Fowler, Peter, Integrated circuit assembly and method of making.
  7. Do, Byung Tai; Trasporto, Arnel Senosa; Chua, Linda Pei Ee, Integrated circuit packaging system with contacts and method of manufacture thereof.
  8. Do, Byung Tai; Trasporto, Arnel Senosa; Chua, Linda Pei Ee, Integrated circuit packaging system with package-on-package and method of manufacture thereof.
  9. Do, Byung Tai; Trasporto, Arnel Senosa; Chua, Linda Pei Ee, Integrated circuit packaging system with terminals and method of manufacture thereof.
  10. Celaya,Phillip C.; Donley,James S.; St. Germain,Stephen C., Lead-free integrated circuit package structure.
  11. Fanelli, Stephen A., Semiconductor device with self-aligned back side features.
  12. Cho,Byeong Yeon; Lee,Hee Seok; Jang,Kyung Lae, Semiconductor package with conductive molding compound and manufacturing method thereof.
  13. Stuber, Michael A.; Molin, Stuart B.; Nygaard, Paul A., Semiconductor-on-insulator with back side body connection.
  14. Nygaard, Paul A.; Molin, Stuart B.; Stuber, Michael A., Semiconductor-on-insulator with back side heat dissipation.
  15. Nygaard, Paul A.; Molin, Stuart B; Stuber, Michael A; Aubain, Max, Semiconductor-on-insulator with back side heat dissipation.
  16. Nygaard, Paul A.; Molin, Stuart B.; Stuber, Michael A., Semiconductor-on-insulator with back side strain inducing material.
  17. Nygaard, Paul A.; Molin, Stuart B.; Stuber, Michael A.; Aubain, Max, Semiconductor-on-insulator with back side strain topology.
  18. Molin, Stuart B.; Nygaard, Paul A.; Stuber, Michael A., Semiconductor-on-insulator with back side support layer.
  19. Molin, Stuart B.; Nygaard, Paul A.; Stuber, Michael A., Semiconductor-on-insulator with back side support layer.
  20. Ichitsubo,Ikuroh; Kubota,Kanya; Kuwano,Masaya; Matsumoto,Koshiro, Systems of miniaturized compatible radio frequency wireless devices.
  21. Stuber, Michael A.; Molin, Stuart B.; Drucker, Mark; Fowler, Peter, Thin integrated circuit chip-on-board assembly.
  22. Stuber, Michael A.; Molin, Stuart B.; Drucker, Mark; Fowler, Peter, Thin integrated circuit chip-on-board assembly and method of making.
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