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A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnect

A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

대표청구항 ▼

1. A method of prioritizing and granting bus access requests in a system that comprises a table of slots assigned to bus masters, wherein the table has a number of slots and one of the slots serves as an access slot, and wherein at least one of the bus masters is assigned to multiple slots in the ta

1. A method of prioritizing and granting bus access requests in a system that comprises a table of slots assigned to bus masters, wherein the table has a number of slots and one of the slots serves as an access slot, and wherein at least one of the bus masters is assigned to multiple slots in the table, the method comprising:(a) granting a bus access request of a bus master asserting a high priority interrupt; (b) if no bus master is asserting a high priority interrupt, determining whether a bus master making a bus access request is currently assigned to the access slot in the table, and granting the bus access request of that bus master if it is determined that the bus master is currently assigned to the access slot in the table; and (c) if no bus master is asserting the high priority interrupt and no bus master making an access request is assigned to the access slot, granting a bus access request of a bus master highest on a round robin priority list. 2. The method of claim 1, wherein the step (a) further comprises:generating the high priority interrupt for a processor operating on a real-time signal when the processor has been in a wait state for a time-out period. 3. The method of claim 2, wherein the time-out period is programmable.4. The method of claim 2, wherein a first bus master is assigned more slots in the table than a second bus master.5. The method of claim 2, wherein the step (b) further comprises:if the bus access request of a bus master assigned the access slot is granted, updating the table so that a different one of the bus master entries in the table is assigned to the access slot. 6. The method of claim 5, further comprising:if the bus access request of a bus master highest on the round robin priority list is granted, updating the round robin priority list and also updating the table so that a different one of the bus master entries in the table is assigned to the access slot. 7. The method of claim 5, further comprising a step of:assigning a number of slots in the table to each bus master based upon the relative bandwidth requirements of the bus masters.