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Performance and power optimization via block oriented performance measurement and control 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-001/32
  • G06F-001/26
출원번호 US-0798176 (2001-03-02)
발명자 / 주소
  • Altmejd, Morrie
  • Menezes, Evandro
  • Tobias, Dave
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Zagorin O'Brien Graham LLP
인용정보 피인용 횟수 : 41  인용 특허 : 29

초록

An integrated circuit includes a plurality of functional blocks. Utilization information for the various functional blocks is generated. Based on that information, the power consumption and thus the performance levels of the functional blocks can be tuned. Thus, when a functional block is heavily lo

대표청구항

1. A method of controlling power consumption in an integrated circuit that includes a plurality of functional blocks, comprising:generating respective block utilization information for the functional blocks included in the integrated circuit; and independently managing power of the respective functi

이 특허에 인용된 특허 (29)

  1. Reinhardt Dennis ; Bhat Ketan ; Jackson Robert T. ; Senyk Borys ; Matter Eugene P. ; Gunther Stephen H., Apparatus and method for controlling power usage.
  2. Andrew David Wallace GB; Christopher Neville Tate GB; Mike Francis Grant GB, Apparatus, method and system having reduced power consumption in a multi-carrier wireline environment.
  3. Cooper, Barnes; Arjangrad, Jay, CPU power management based on utilization with lowest performance mode at the mid-utilization range.
  4. Arai Makoto,JPX ; Oda Hiroyuki,JPX ; Ito Hironori,JPX, Cooling mode switching system for CPU.
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  6. Roden Philip A. ; Neil Patrick C. ; Rekieta David W., Dynamic device power management.
  7. Atkinson Lee W., Increased processor performance comparable to a desktop computer from a docked portable computer.
  8. Kawata Kaoru,JPX, Information processing apparatus with CPU-load-based clock frequency.
  9. Buxton Clark L. ; Craycraft Donald G. ; Hawkins Keith G. ; Baum Gary, Integrated processor system adapted for portable personal information devices.
  10. Groezinger Gerhard (Spaichingen DEX), Measuring apparatus for determining the degree of utilization of a machine.
  11. Grochowski, Edward T.; Sager, David; Tiwari, Vivek; Young, Ian; Ayers, David J., Mechanism to control di/dt for a microprocessor.
  12. Kou James, Method and apparatus for a computer power management function including selective sleep states.
  13. Hetherington Ricky C. ; Panwar Ramesh, Method and apparatus for moderating current demand in an integrated circuit processor.
  14. Bikowsky Zeev,ILX, Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down.
  15. Simmons Laura E. ; Jayavant Rajeev, Method and apparatus for reducing power consumption in digital electronic circuits.
  16. Horden A. Ira ; Gorman Steven D. ; Smith Lionel S., Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control pow.
  17. Grochowski, Edward T.; Sharma, Vinod; Matthews, Gregory S.; Joshi, Vivek; Kling, Ralph M., Microprocessor with digital power throttle.
  18. Mittal Millind ; Valentine Robert,ILX, Performance throttling to reduce IC power consumption.
  19. Cathey David A., Portable computer with selectively operable cooling unit.
  20. Anderson Eric Christopher ; Farhi Henri Hayim, Power management inactivity monitoring using software threads.
  21. Wisor Michael T. (Austin TX) O\Brien Rita M. (Austin TX), Power management system distinguishing between primary and secondary system activity.
  22. Evoy David R. ; Hicok Gary D. ; Simmons Laura E., Power management system for a computer.
  23. Iwazaki Yasuo,JPX, Power-saving clock control apparatus and method.
  24. Vea Matthew J. J. (Rowlett TX), Real time digital signal processor idle indicator.
  25. Locklear ; Jr. Robert H. ; Cantrell Craig S. ; McClanahan Kip R. ; Brewer William K. ; Carew Anthony J. P., Switched architecture access server.
  26. Lin Richard S. ; Maguire David J. ; Edwards James R. ; Delisle David J., System incorporating hot docking and undocking capabilities without requiring a standby or suspend mode by placing local.
  27. Halahmi Dror,ILX ; Zmora Eitan,ILX ; Goldenberg Chen,ILX, System power saving means and method.
  28. Barnes Cooper, Thermal control within systems having multiple CPU performance states.
  29. Barrus Jeff, User-selectable power management interface with application threshold warnings.

이 특허를 인용한 특허 (41)

  1. Hsu,Hsien Yueh, Apparatus and method for real-time adjusting system performance of a computer.
  2. Das, Rajarshi; Vitale, Philip L, Calculating the clock frequency of a processor.
  3. Hamilton,Tony G., Computing device with scalable logic block to respond to data transfer requests.
  4. May,Marcus W.; Mulligan,Daniel, Conserving power of a system on a chip using speed sensing.
  5. Kolinummi,Pasi; Vehvil채inen,Juhani, Dynamic power control in integrated circuits.
  6. Lee, Jong Pil, Dynamically scaling apparatus for a system on chip power voltage.
  7. Lee, Jong Pil, Dynamically scaling apparatus for a system on chip power voltage.
  8. Fatemi, Hamed; Kapoor, Ajay; Pineda de Gyvez, Jose, Energy efficient microprocessor platform based on instructional level parallelism.
  9. Prasek, Phil; Nazarov, Alex; Kar, Swayambhuba, Estimating power consumption for a target host.
  10. Manne, Srilatha; Desikan, Rajagopalan; Pant, Sanjay; Kim, Youngtaek, Guardband reduction for multi-core data processor.
  11. Gunther, Stephen H.; Burton, Edward A.; Deval, Anant; Jourdan, Stephan; Greiner, Robert; Cornaby, Michael, Independent power control of processing cores.
  12. Gunther, Stephen H.; Burton, Edward A.; Deval, Anant; Jourdan, Stephan; Greiner, Robert; Cornaby, Michael, Independent power control of processing cores.
  13. Gunther, Stephen H.; Burton, Edward A.; Deval, Anant; Jourdan, Stephan; Greiner, Robert; Cornaby, Michael, Independent power control of processing cores.
  14. Meijer, Rinze Ida Mechtildis Peter; Al-kadi, Ghiath, Integrated circuit.
  15. Singh,Jitendra K., Managing power consumption based on utilization statistics.
  16. Fleck, Rod G.; Flynn, Rex Antony; Kee, Martin J.; Perrin, Stephen L., Method and apparatus for operating an electronic device in a low power mode with a low power mode application based on determined operating parameters.
  17. Garritsen,Frido; Chen,Julia; Chang,Terry, Method and apparatus for reducing power consumption in a graphics controller.
  18. Prasek, Phil; Nazarov, Alex; Kar, Swayambhuba, Method and system for estimating power consumption for aggregate system workload.
  19. Drescher, Wolfram, Method for effecting the controlled shutdown of data processing units.
  20. Cooper,Barnes; Kobayashi,Grant H., Method for managing virtual and actual performance states of logical processors in a multithreaded processor using system management mode.
  21. Cooper,Barnes; Kobayashi,Grant H., Method for providing power management on multi-threaded processor by using SMM mode to place a physical processor into lower power state.
  22. Lyu, Young-Ki, Method of power management for dynamically controlling power in a processor in according to a workload rate of the processor.
  23. Nijhawan, Vijay B.; Darnell, Gregory N.; Wu, Wuxian, Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold.
  24. Gary,Scott P.; Cyran,Robert J.; Sarathy,Vijaya B. P., Methods and systems for performing dynamic power management via frequency and voltage scaling.
  25. Gunther, Stephen H.; Burton, Edward; Deval, Anant; Jourdan, Stephan; Greiner, Robert; Cornaby, Mike, Operating integrated circuit logic blocks at independent voltages with single voltage supply.
  26. Arabi, Tawfik; Muhtaroglu, Ali; Bitan, Michael, Per die voltage programming for energy efficient integrated circuit (IC) operation.
  27. Flautner,Krisztian; Mudge,Trevor Nigel, Performance level selection in a data processing system by combining a plurality of performance requests.
  28. Flautner,Krisztian; Mudge,Trevor Nigel, Performance level selection in a data processing system using a plurality of performance request calculating algorithms.
  29. Naffziger, Samuel; Liu, Baomin; Touzelbaev, Maxat, Performance state boost for multi-core integrated circuit.
  30. Manne, Srilatha; Pant, Sanjay; Kim, Youngtaek; Schulte, Michael J., Power control for multi-core data processor.
  31. Niggemeier, Tim; Barowski, Harry; Boersma, Maarten; Spiess, Gunnar, Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independent.
  32. Cha, Hungse; Hasslen, III, Robert J.; Robinson, John A.; Treichler, Sean J.; Diril, Abdulkadir Utku, Power estimation based on block activity.
  33. Morgan, Bryan C.; Vaidya, Priya N.; Sakarda, Premanand; Moncrieffe, Marlon A., Power management in electronic systems.
  34. Hoberman, Barry Alan; Hillman, Daniel L.; Shiell, Jon, Power managers for an integrated circuit.
  35. Hoberman, Barry Alan; Hillman, Daniel L.; Shiell, Jon, Power managers for an integrated circuit.
  36. Wu, Te-Lung; Lee, Chun-Da; Chen, Chien-Liang, Power signal detecting system, method and a portable electronic device thereof.
  37. Krieger, Orran Y.; Rosenburg, Bryan S.; Sinharoy, Balaram; Tremaine, Robert B.; Wisniewski, Robert W., Scheduling threads having complementary functional unit usage on SMT processors.
  38. Chun, Dexter T; Wolf, Jack K; Suh, Jungwon; Sowlati, Tirdad, SerDes power throttling as a function of detected error rate.
  39. Vaidya,Priya N; Sakarda,Premanand; Morgan,Bryan C; Ge,Yi, System and method for adaptive power management.
  40. Morgan, Bryan C; Sakarda, Premanand; Vaidya, Priya N; Ge, Yi; Gao, Zhou; Pang, Swee-chin; Thadani, Manoj I; Yuan, Canhui, System and method for adaptive power management based on processor utilization and cache misses.
  41. Morgan, Bryan C.; Vaidya, Priya N.; Sakarda, Premanand; Moncrieffe, Marlon A., System for managing power provided to a processor or memory based on a measured memory consumption characteristic.
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