IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0833112
(2004-04-28)
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발명자
/ 주소 |
- Dakshina-Murthy, Srikanteswara
- An, Judy Xilin
- Krivokapic, Zoran
- Wang, Haihong
- Yu, Bin
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출원인 / 주소 |
- Advanced Micro Devices, Inc.
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
70 인용 특허 :
4 |
초록
▼
A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induc
A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.
대표청구항
▼
1. A semiconductor device, comprising:a fin comprising a first semiconducting material; and a first layer formed on at least a portion of the fin, wherein the first semiconducting material induces tensile strain within the first layer and wherein a thickness of the first layer ranges from approximat
1. A semiconductor device, comprising:a fin comprising a first semiconducting material; and a first layer formed on at least a portion of the fin, wherein the first semiconducting material induces tensile strain within the first layer and wherein a thickness of the first layer ranges from approximately 3.3 nm to 7.5 nm. 2. The device of claim 1, wherein a thickness of the fin ranges from about 500 Å to about 2000 Å.3. The device of claim 1, wherein the fin has a width ranging from approximately 10 nm to 15 nm.4. The semiconductor device of claim 1, wherein the first layer comorises a second semiconducting material and wherein the second semiconducting material comprises silicon.5. The semiconductor device of claim 4, wherein the first semiconducting material comprises SixGe(1-x).6. The semiconductor device of claim 5, wherein x equals approximately 0.7.7. The semiconductor device of claim 1, further comprising:a second layer formed on at least a portion of the first layer, the second layer comprising a dielectric. 8. The semiconductor device of claim 7, further comprising:a gate electrode formed on at least a portion of the second layer, the gate electrode comprising polysilicon. 9. A transistor, comprising:a fin comprising a first semiconducting material that has a first lattice constant, the fin further comprising first and second end portions; source and drain regions formed adjacent the first and second end portions of the fin; a first layer of second semiconducting material formed on at least a portion of the fin, the second semiconducting material having a second lattice constant, wherein the first lattice constant is greater than the second lattice constant and wherein the first layer has a thickness ranging from about 3.3 nm to about 7.5 nm; a dielectric layer formed on at least a portion of the first layer; and a gate electrode formed on at least a portion of the dielectric layer. 10. The transistor of claim 9, wherein the fin has a width ranging from approximately 10 nm to 15 nm.11. The transistor of claim 9, wherein the first layer has a thickness ranging from ½ to ⅓ of the fin width.12. The transistor of claim 9, wherein a thickness of the fin ranges from about 500 Å to about 2000 Å.13. The transistor of claim 9, wherein the gate electrode comprises a third semiconducting material.14. The transistor of claim 13, wherein the third semiconducting material comprises polysilicon.15. The transistor of claim 9, wherein the first semiconducting material comprises SixGe(1-x).16. The transistor of claim 15, wherein the second serniconducting material comprises silicon.17. The transistor of claim 16, wherein x equals approximately 0.7.18. The transistor of claim 9, wherein the first layer comprises a strained layer and wherein tensile strain in the strained layer increases carrier mobility in the fin.19. The device of claim 1, wherein the first layer comprises a second semiconducting material and wherein the first semiconducting material has a larger lattice constant than the second semiconducting material to induce the tensile strain within the first layer.20. A semiconductor device, comprising:a fin comprising a first semiconducting material and a plurality of surfaces, wherein the fin comprises a width ranging from approximately 10 nm to 15 nm; and a first layer formed on at least a portion of the plurality of surfaces, the first layer comprising a second semiconducting material, wherein the first semiconducting material has a different lattice constant than the second semiconducting material to induce tensile strain within the first layer and wherein the first layer comorises a thickness that is approximately ½ to ⅓ of the fin width. 21. The semiconductor device of claim 20, wherein the first semiconducting material comprises a semiconducting material with a lattice constant larger than a lattice constant of the second semiconducting material.22. A transistor, comprising:a fin comprising a first semiconducting material that has a first lattice constant, the fin further comprising first and second end portions and a width; source and drain regions formed adjacent the first and second end portions of the fin; a first layer of second semi-conducting material formed on at least a portion of the fin, the second semiconducting material having a second lattice constant, wherein the first lattice constant is greater than the second lattice constant and wherein the first layer comprises a thickness that is approximately ½ to ⅓ of the fin width; a dielectric layer formed on at least a portion of the first layer; and a gate electrode formed on at least a portion of the dielectric layer. 23. The transistor of claim 22, wherein the gate electrode comprises a third semiconducting material.24. The transistor of claim 22, wherein the first lattice constant is greater than the second lattice constant to induce tensile strain in the first layer.25. The transistor of claim 22, wherein the width ranges from approximately 10 nm to 15 nm.26. A method of forming a semiconductor device, comprising:forming a fin comprising a first semiconducting material, a plurality of surfaces, and a width; and forming a first layer on at least a portion of the plurality of surfaces, the first layer comprising a second semiconducting material, wherein the first semiconducting material is lattice constant mismatched with the second semiconducting material to induce tensile strain within the first layer and wherein the first layer comprises a thickness that is approximately ½ to ⅓ of the fin width. 27. The method of claim 26, further comprising:selecting the first semiconducting material such that the first semiconducting material has a lattice constant greater than a lattice constant of the second seiniconducting material. 28. The method of claim 26, wherein the width of the fin ranges from approximately 10 nm to 15 nm.
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