IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0397021
(2003-03-24)
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발명자
/ 주소 |
- Dugger, Jeffery Don
- Hall, Tyson S.
- Hasler, Paul
- Anderson, David V.
- Smith, Paul D.
- Kucic, Matthew Raymond
- Bandyopadhyay, Abhishek
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출원인 / 주소 |
- Georgia Tech Research Corp.
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대리인 / 주소 |
Thomas, Kayden, Horstemeyer &
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인용정보 |
피인용 횟수 :
15 인용 특허 :
7 |
초록
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In one exemplary embodiment, a programmable analog array (PAA) contains a configurable analog matrix having two floating-gate field effect transistors (FETs). Also contained in the PAA is an interconnect circuit that is programmable to configure the configurable analog matrix to operate in one or mo
In one exemplary embodiment, a programmable analog array (PAA) contains a configurable analog matrix having two floating-gate field effect transistors (FETs). Also contained in the PAA is an interconnect circuit that is programmable to configure the configurable analog matrix to operate in one or more of several matrix modes. A few examples of such matrix modes include a switching matrix mode, a memory matrix mode, and a computing matrix mode. In an exemplary method of configuring the PAA. PAA, the the method includes programming an interconnection, for example, between a first terminal of the first floating-gate FET and a first terminal of the second floating-gate FET. The method further includes programming an interconnection, for example, between a gate terminal of the first floating-gate FET and a fixed voltage source, for setting a floating gate charge on the first floating-gate FET.
대표청구항
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1. An image processing circuit comprising:a signal generator configured to generate a time basis signal; an optical sensor element comprising a differential pair of transistors and an optical sensor diode, the optical sensor element configured to receive the time basis signal and an input optical si
1. An image processing circuit comprising:a signal generator configured to generate a time basis signal; an optical sensor element comprising a differential pair of transistors and an optical sensor diode, the optical sensor element configured to receive the time basis signal and an input optical signal, and further configured to generate a differential output electrical signal that is proportional to the product of an amplitude of the time basis signal at a first instance in time and an amplitude of the input optical signal at the first instance in time; an analog computing element comprising a floating-gate pFET configured to perform a mathematical transform operation upon the differential output electrical signal from the optical sensor element at the first instance in time; and an interconnect circuit that is programmable to provide an interconnection between the differential pair of transistors and the optical sensor diode, is programmable to provide an interconnection between the differential pair of transistors and a gate terminal of the floating-gate pFET, and is further programmable to provide a floating charge in the floating-gate pFET of the analog computing element. 2. The image processing circuit of claim 1, wherein the analog computing element comprises an array of floating-gate pFETs, and wherein the floating-gate pFET is a part of the array of floating-gate pFETs.3. The image processing circuit of claim 2, wherein the floating-gate pFET is configured to operate as an analog memory element upon providing the floating charge into the floating-gate of the floating-gate pFET.4. The image processing circuit of claim 2, wherein the mathematical transform operation comprises multiplying the output electrical signal from the optical sensor element by a weight, and wherein the weight is proportional to the floating charge that is programmed into the floating-gate of the floating-gate pEET.5. A cepstral processor, comprising:a programmable bandpass filter configured to provide a programmable frequency response to an input signal that is coupled into the programmable bandpass filter; a programmable peak detector that is programmed using a control voltage to provide a user-selectable frequency response; a programmable analog memory comprising a floating-gate pFET, the floating-gate pFET configured to provide a programmable analog memory value, the programmable analog memory communicatively coupled to the programmable bandpass filter; and an interconnect circuit that is programmable to provide the communicative coupling between the programmable analog memory and the programmable bandpass filter, and is further programmable to provide a floating charge in the floating-gate pFET, the floating charge being the programmable analog memory value. 6. The cepstral processor of claim 5, wherein the programmable analog memory comprises an array of floating-gate pFETs, and wherein the floating-gate pFET is a part of the array of floating-gate pFETs.7. The cepstral processor of claim 6, wherein the floating-gate pFET is configured to operate as an analog computing element by programming a charge into the floating-gate of the floating-gate pFET.8. The cepstral processor of claim 6, wherein the programmable bandpass filter is a capacitively coupled current conveyor circuit.9. A programmable analog array (PAA) comprising:a configurable analog matrix having a first floating-gate field effect transistor (FET) and a second floating-gate FET, the configurable analog matrix being configurable to operate in one of a plurality of matrix modes; and an interconnect circuit that is programmable to configure the configurable analog matrix to operate in the one of a plurality of matrix modes, and wherein the interconnect circuit is further programmable to provide a floating charge in at least one of the first and second floating-gate FETs. 10. The PAA of claim 9, wherein the plurality of matrix modes comprises one of a switching matrix mode, a memory matrix mode, and a computing matrix mode.11. The PAA of claim 10, wherein the interconnect circuit is further programmable to interconnect a first terminal of the first floating-gate FET to at least one of a first terminal of the second floating-gate FET, an input pin of the PAA, an output pin of the PAA, a voltage supply, and a ground connection.12. The PAA of claim 11, wherein the interconnect circuit is further programmable to interconnect a gate terminal of the first floating-gate FET to one of a fixed voltage source and the ground connection for setting a floating gate charge on the first floating-gate FET.13. The PAA of claim 10, wherein the switching matrix mode comprises at least one of the first and second floating-gate FETs operating as an analog switching element of the configurable analog matrix.14. The PAA of claim 10, wherein the memory matrix mode comprises at least one of the first and second floating-gate FETs operating as an analog memory element of the configurable analog matrix.15. The PAA of claim 10, wherein the computing matrix mode comprises at least one of the first and second floating-gate FETs operating as an analog computing element of the configurable analog matrix.16. The PAA of claim 15, wherein the analog computing element provides an analog multiplication function comprising an input signal multiplied by a floating-gate charge programmed into the at least one of the first and second floating-gate FETs.17. The PAA of claim 9, wherein the interconnect circuit comprises at least one of an analog switch, a digital switch, and a fusible link.18. A method of configuring a programmable analog array (PAA), the method comprising:providing in the PAA, a configurable analog matrix having a first floating-gate field effect transistor (FET) and a second floating-gate FET, the configurable analog matrix being configurable to operate in one of a plurality of matrix modes; programming an interconnection between a first terminal of the first floating-gate field effect transistor (FET) and at least one of a first terminal of the second floating-gate FET, an input pin of the PAA, an output pin of the PAA, a voltage supply, and a ground connection; and programming an interconnection between a gate terminal of the first floating-gate FET and one of a fixed voltage source and the ground connection for setting a floating gate charge on the first floating-gate FET. 19. The method of claim 18, the method further comprising: operating the PAA in a matrix mode comprising one of a switching matrix mode, a memory matrix mode, and a computing matrix mode.
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