IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0306719
(2002-11-27)
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발명자
/ 주소 |
- Muegge, Mark R.
- Eason, Mark
- Telefus, Mark D.
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
61 인용 특허 :
42 |
초록
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A method of regulating voltage at an output of a switching power converter includes sensing an output voltage feedback signal; comparing the sensed feedback signal to a reference at a determined time during a cycling of the switch; and regulating the output voltage by either enabling or inhibiting c
A method of regulating voltage at an output of a switching power converter includes sensing an output voltage feedback signal; comparing the sensed feedback signal to a reference at a determined time during a cycling of the switch; and regulating the output voltage by either enabling or inhibiting cycling of a switch by a cycle of a drive signal produced by pulse generation circuitry in response to an output of the comparison.
대표청구항
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1. A method of regulating voltage at an output of a switching power converter, the converter comprising a switch and pulse modulating control circuitry, the pulse modulating control circuitry producing power pulses for cycling the switch ON and OFF, wherein if the switch is cycled ON and OFF accordi
1. A method of regulating voltage at an output of a switching power converter, the converter comprising a switch and pulse modulating control circuitry, the pulse modulating control circuitry producing power pulses for cycling the switch ON and OFF, wherein if the switch is cycled ON and OFF according to a power pulse cycle, power is transferred from a source to a load, the method comprising:sensing an output voltage feedback signal; using a comparator to compare the sensed feedback signal to a reference at a determined time during a cycling of the switch; and regulating the output voltage by controlling turn ON and turn OFF times of the switch in response to an output of the comparator, wherein determining the turn ON and turn OFF times of the switch in response to a present comparison is based at least in part on comparisons of the sensed feedback signal to the reference made during one or more previous switch cycles. 2. A method of regulating power between a source and a load, comprising:providing a power converter, the converter comprising a switch and pulse modulating control circuitry, the pulse modulating control circuitry producing power pulses for cycling the switch ON and OFF, wherein if the switch is cycled ON and OFF according to a power pulse cycle, power is transferred from the source to the load; sensing an output voltage feedback signal originating from a primary side of the converter, the sensed feedback signal approximating an output voltage at the load; using a comparator to compare the sensed feedback signal to a reference at an instant at which the sensed feedback signal corresponds to the output voltage at the load plus a small, substantially constant voltage drop measured from cycle to cycle of the switch; and regulating the output voltage by controlling turn ON and turn OFF times of the switch in response to an output of the comparator, wherein comparator outputs from one or more previous switch cycles are used in determining the turn ON and turn OFF times of the switch in response to a present comparator output. 3. A method of regulating voltage at an output of a switching power converter, comprising:sensing an output voltage feedback signal; using a comparator to compare the sensed feedback signal to a reference; using an early/late detector to detect transitions of an output of the comparator relative to an expected transition time within a switching cycle; and regulating the output voltage by controlling turn ON and turn OFF times of a switch in response to an output of the early/late detector. 4. The method of claim 3, wherein the expected transition time is determined at each cycling of the switch.5. The method of claim 3, wherein the expected transition time is an instant at which the output voltage feedback signal corresponds to the output voltage at a load plus a small, substantially constant voltage drop measured from cycle to cycle of the switch.6. The method of claim 3, wherein the expected transition time is an instant at which current flowing through a secondary rectifying element is small and substantially constant from cycle to cycle of the switch.7. The method of claim 3, wherein the converted is a flyback converter having a transformer flux reset point, the output voltage feedback signal is a reflected flyback voltage signal, and the expected transition time is at a fixed backward offset time from the transformer flux reset point.8. The method of claim 3, wherein early/late detector outputs from one or more previous switch cycles are used in determining the turn ON and turn OFF times of the switch in response to a present early/late detector output.9. The method of claim 3, wherein the converter is a forward converter having an output inductor, the output voltage feedback signal is a reflected voltage across an auxiliary winding coupled to the output inductor, and the expected transition time is a fixed backward offset time from a point of output inductor flux reset.10. The method of claim 3, wherein the converter is a direct-coupled boost converter, the output voltage feedback signal corresponds to a voltage across the switch during its OFF time, and the expected transition time in an instant at which current through a rectifying element is small and substantially constant from cycle to cycle of the switch.11. The method of claim 3, wherein the converter is a direct-coupled buck converter, the output voltage feedback signal corresponds to a differential voltage across an output inductor during the OFF time of the switch, and the expected transition time is at an instant at which current through a rectifying element is small and substantially constant from cycle to cycle of the switch.12. A method of claim 3, wherein the turn ON times are controlled to coincide with instants at which voltage across the switch is a minimum.13. A method of regulating voltage at an output of a switching power converter, the converter comprising a switch and pulse modulating control circuitry, the pulse modulating control circuitry producing power pulses for cycling the switch ON and OFF, wherein if the switch is cycled ON and OFF according to a power pulse cycle, power is transferred from a source to a load, the method comprising:sensing an output voltage feedback signal originating from a primary side of the converter, the sensed feedback signal approximating an output voltage at the load; using a comparator to compare the sensed feedback signal to a reference; using an early/late detector to detect transitions of an output of the comparator relative to an instant at which the sensed feedback signal corresponds to the output voltage at the load plus a small, substantially constant voltage drop measured from cycle to cycle of the switch; and regulating the output voltage by controlling turn ON and turn OFF times of the switch in response to an output of the early/late detector. 14. The method of claim 13, wherein early/late detector outputs from one or more previous switch cycles are used in determining one or both of the turn ON time and turn OFF time of the switch in response to a present early/late detector output.15. The method of claim 13, wherein the early/late detector is one of a binary detector, a ternary detector, and a signed digital detector.16. The method of claim 13, wherein the early/late detector is a binary detector, wherein crossover of the output voltage feedback signal with the reference is signaled by a transition of a binary comparator, and monitoring whether the comparator transition occurs within a specified period of time.17. The method of claim 13, the early/late detector comprising a ternary detector wherein crossover of the output voltage feedback signal with the reference is signaled by a transition of a binary comparator, the method further comprising:starting a timer at an earlier of a comparator transition time or an expected transition time, and terminating the timer upon later of the comparator transition time, the expected transition time, or a timeout of the timer.
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