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A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a thi

A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in response to changes in temperature.

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1. A biasing circuit comprising:a first circuit configured to generate a first bias signal and a second bias signal, wherein said second bias signal is defined by a threshold voltage and a first resistance; and a second circuit configured to generate a third bias signal in response to said first and

1. A biasing circuit comprising:a first circuit configured to generate a first bias signal and a second bias signal, wherein said second bias signal is defined by a threshold voltage and a first resistance; and a second circuit configured to generate a third bias signal in response to said first and second bias signals and a second resistance, wherein said third bias signal has a magnitude that is linearly proportional to absolute temperature (PTAT) and is configured to vary a refresh rate of a memory cell in response to changes in temperature. 2. The biasing circuit according to claim 1, wherein said biasing circuit comprises a proportional to temperature voltage generator.3. The biasing circuit according to claim 1, wherein said first circuit comprises:a first current source configured to generate a first proportional to absolute temperature (PTAT) current, said first PTAT current defined by a first threshold voltage; a second current source configured to generate a second PTAT current in response to said first PTAT current, said second PTAT current defined by a second threshold voltage, a ratio of diode areas and said first resistance; and a control circuit configured to equalize said first PTAT current and said second PTAT current. 4. The biasing circuit according to claim 1, wherein said second circuit comprises:a current source configured to generate a PTAT current that varies linearly with temperature. 5. The biasing circuit according to claim 1, wherein a voltage magnitude of said third bias signal is determined by a ratio of said second resistance to said first resistance.6. The biasing circuit according to claim 1, wherein said second bias signal comprises a bandgap reference voltage.7. The biasing circuit according to claim 1, wherein said first circuit comprises:a first current mirror comprising a plurality of PMOS transistors; a second current mirror comprising a plurality of NMOS transistors, said second current mirror coupled to said first current mirror; a first diode coupled directly to said second current mirror; and a second diode coupled through a resistor to said second current mirror. 8. The circuit according to claim 1, wherein said second circuit further comprises a voltage mirror configured to generate a fourth bias signal in response to said third bias signal.9. The biasing circuit according to claim 3, wherein said control circuit comprises:an operational amplifier coupled to said first current source and said second current source and configured to equalize said first PTAT current and said second PTAT current. 10. A circuit for generating temperature sensitive biasing of a voltage controlled oscillator (VCO) comprising:a first circuit configured to generate a first bias signal and a second bias signal, wherein said second bias signal is defined by a threshold voltage and a first resistance; and a second circuit configured to generate one or more third bias signals in response to said first and second bias signals and a second resistance, wherein said one or more third bias signals have a magnitude that is linearly proportional to absolute temperature (PTAT) and vary a refresh rate of a memory cell with temperature. 11. The circuit according to claim 10, wherein said one or more third bias signals provides load bias voltages to a plurality of delay stages of said voltage controlled oscillator.12. The circuit according to claim 10, wherein said voltage controlled oscillator is configured to generate a signal having a frequency that varies with temperature.13. The circuit according to claim 12, wherein said frequency varies linearly with temperature.14. The circuit according to claim 12, wherein said frequency variation is proportional to absolute temperature.15. A method for controlling a refresh rate of a memory using a proportional to absolute temperature (PTAT) voltage reference comprising the steps of:(A) generating a first bias signal; (B) generating a second bias signal in response to said first bias signal, wherein said second bias signal is defined by a threshold voltage and a first resistance; and (C) generating a third bias signal in response to said first and second bias signals and a second resistance, wherein said third bias signal has a magnitude that is linearly proportional to absolute temperature (PTAT) and is configured to vary a refresh rate of a memory cell with temperature. 16. The method according to claim 15, wherein step A comprises the sub-steps of:generating a first PTAT current; generating a second PTAT current; and adjusting said first bias signal to equalize said first and second PTAT currents. 17. The method according to claim 15, wherein the step C comprises the sub-steps of:generating a PTAT current in response to said first bias signal and said second bias signal; and passing said PTAT current through said second resistance. 18. The method according to claim 15, further comprising the step of:presenting said third bias signal to a memory circuit to control a refresh rate. 19. The method according to claim 18, wherein said presenting step comprises the sub-step of:generating a signal having a frequency that increases linearly with temperature. 20. The method according to claim 19, wherein said increase is proportional to absolute temperature.