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Method and apparatus for electro-chemical mechanical deposition 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C25F-003/16
출원번호 US-0238665 (2002-09-09)
발명자 / 주소
  • Talieh, Homayoun
출원인 / 주소
  • ASM Nutool, Inc.
대리인 / 주소
    Knobbe, Martens, Olson &
인용정보 피인용 횟수 : 34  인용 특허 : 19

초록

The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surfa

대표청구항

1. A method of polishing a conductive material from a top surface of a wafer using a pad, a solution and an electrode electrically coupled to the solution, wherein the top surface of the wafer further includes a cavity portion, comprising the steps of:positioning the pad in close proximity to the to

이 특허에 인용된 특허 (19)

  1. Leppnen YrjT. J. (Pori FIX), Apparatus for electrolytic polishing.
  2. Brusic Vlasta A. ; Marino Jeffrey Robert ; O'Sullivan Eugene John ; Sambucetti Carlos Juan ; Schrott Alejandro Gabriel ; Uzoh Cyprian Emeka, Cobalt-tin alloys and their applications for devices, chip interconnections and packaging.
  3. Seimiya Kouichi (Sakura JPX) Nakagami Kenji (Ayase JPX), Combined electrolytic-abrasive polishing apparatus.
  4. Uzoh Cyprian E., Continuous highly conductive metal wiring structures and method for fabricating the same.
  5. Palnik Karl (Huntingdon Valley PA), Electrolytic plating apparatus.
  6. Steblianko Valerij Leontievich (Magnitogorsk RUX) Riabkov Vitalij Makrovich (Moscow RUX), Electrolytic process for cleaning and coating electrically conducting surfaces.
  7. Dubin Valery, Electroplating apparatus.
  8. Ichinose Hirofumi,JPX ; Sawayama Ippei,JPX ; Hasebe Akio,JPX ; Murakami Tsutomu,JPX ; Hisamatsu Masaya,JPX ; Shinkura Satoshi,JPX ; Ueno Yukie,JPX, Etching method and process for producing a semiconductor element using said etching method.
  9. Talieh Homayoun (Santa Clara County CA) Weldon David Edwin (Santa Cruz County CA), Linear polisher and method for semiconductor wafer planarization.
  10. Talieh Homoyoun (Sunnyvale CA) Tepman Avi (Cupertino CA) Kieu Hoa Thi (Sunnyvale CA) Wang Chien-Rhone (Milpitas CA), Material deposition method for integrated circuit manufacturing.
  11. Kadija Igor V. (118 Sherwood Rd. Ridgewood NJ 07450), Method and apparatus for manufacturing interconnects with fine lines and spacing.
  12. Adams John A. ; Krulik Gerald A. ; Smith Everett D., Method for simultaneous non-contact electrochemical plating and planarizing of semiconductor wafers using a bipiolar electrode assembly.
  13. Uzoh Cyprian Emeka ; Harper James McKell Edwin, Method of electrochemical mechanical planarization.
  14. Kosaki Katsuya,JPX ; Tamaki Masahiro,JPX, Method of plating semiconductor wafer and plated semiconductor wafer.
  15. Liu Yauh-Ching ; Perng Dung-Ching, Method of single step damascene process for deposition and global planarization.
  16. Simon Andrew H. ; Uzoh Cyprian E., Open-bottomed via liner structure and method for fabricating same.
  17. Ishida Hirofumi (Kanagawa JPX), Plating device for wafer.
  18. Watts John D. (2 Mohawk Drive Clinton CT 06413), Surface finishing and plating method.
  19. Talieh Homayoun (San Jose CA) Weldon David E. (Los Gatos CA) Nagorski Boguslaw A. (San Jose CA), Wafer polishing machine with fluid bearings.

이 특허를 인용한 특허 (34)

  1. Talieh,Homayoun, Apparatus for electroprocessing a workpiece surface.
  2. Ashjaee,Jalal; Nagorski,Boguslaw; Basol,Bulent M.; Talieh,Homayoun; Uzoh,Cyprian, Apparatus for processing surface of workpiece with small electrodes and surface contacts.
  3. Talieh,Homayoun; Uzoh,Cyprian; Basol,Bulent M., Device providing electrical contact to the surface of a semiconductor workpiece during processing.
  4. Talieh,Homayoun; Uzoh,Cyprian; Basol,Bulent M., Device providing electrical contact to the surface of a semiconductor workpiece during processing.
  5. Talieh,Homayoun; Uzoh,Cyprian; Basol,Bulent M., Device providing electrical contact to the surface of a semiconductor workpiece during processing.
  6. Basol, Bulent M.; Bogart, Jeffrey, Electrode and pad assembly for processing conductive layers.
  7. Sun,Lizhong; Liu,Feng Q.; Neo,Siew; Tsai,Stan; Chen,Liang Yuh, Electrolyte with good planarization capability, high removal rate and smooth surface finish for electrochemically controlled copper CMP.
  8. Wang,Yan; Liu,Feng Q.; Duboust,Alain; Neo,Siew S.; Chen,Liang Yuh; Hu,Yongqi, Hydrogen bubble reduction on the cathode using double-cell designs.
  9. Talieh,Homayoun; Basol,Bulent, Method and apparatus for forming an electrical contact with a semiconductor substrate.
  10. Basol,Bulent M., Method and apparatus for localized material removal by electrochemical polishing.
  11. Mayer, Steven T.; Drewery, John S., Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation.
  12. Vasilev, Vladislav, Method and apparatus for workpiece surface modification for selective material deposition.
  13. Vasilev, Vladislav, Method and apparatus for workpiece surface modification for selective material deposition.
  14. Liu,Feng Q.; Du,Tianbao; Duboust,Alain; Hsu,Wei Yung, Method and composition for electrochemical mechanical polishing processing.
  15. Liu,Feng Q.; Du,Tianbao; Duboust,Alain; Wang,Yan; Hu,Yongqi; Tsai,Stan D.; Chen,Liang Yuh; Tu,Wen Chiang; Hsu,Wei Yung, Method and composition for polishing a substrate.
  16. Liu,Feng Q.; Tsai,Stan D.; Hu,Yongqi; Neo,Siew S.; Wang,Yan; Duboust,Alain; Chen,Liang Yuh, Method and composition for polishing a substrate.
  17. Basol, Bulent M., Method for controlling conductor deposition on predetermined portions of a wafer.
  18. Mayer,Steven T.; Reid,Jonathan D.; Rea,Mark L.; Emesh,Ismail T.; Meinhold,Henner W.; Drewery,John S., Method for planar electroplating.
  19. Talieh,Homayoun; Uzoh,Cyprian; Basol,Bulent M., Method of making rolling electrical contact to wafer front surface.
  20. Reid, Jonathan; Varadarajan, Sesha; Emekli, Ugur, Methods and apparatus for depositing copper on tungsten.
  21. Reid, Jonathan; Varadarajan, Sesha; Emekli, Ugur, Methods and apparatus for depositing copper on tungsten.
  22. Mayer, Steven T.; Porter, David W., Modulated metal removal using localized wet etching.
  23. Uzoh,Cyprian; Basol,Bulent; Talieh,Homayoun, Pad designs and structures for a versatile materials processing apparatus.
  24. Mayer, Steven T.; Drewery, John Stephen; Webb, Eric G., Photoresist-free metal deposition.
  25. Basol,Bulent, Plating by creating a differential between additives disposed on a surface portion and a cavity portion of a workpiece.
  26. Basol, Bulent M., Plating method and apparatus for controlling deposition on predetermined portions of a workpiece.
  27. Basol, Bulent M., Plating method and apparatus for controlling deposition on predetermined portions of a workpiece.
  28. Basol, Bulent M., Plating methods for low aspect ratio cavities.
  29. Talieh,Homayoun; Uzoh,Cyprian; Basol,Bulent M., Providing electrical contact to the surface of a semiconductor workpiece during processing.
  30. Mayer, Steven T.; Drewery, John S.; Hill, Richard S.; Archer, Timothy M.; Kepten, Avishai, Selective electrochemical accelerator removal.
  31. Mayer, Steven T.; Drewery, John; Hill, Richard S.; Archer, Timothy; Kepten, Avishai, Selective electrochemical accelerator removal.
  32. Mayer, Steven T.; Stowell, Marshall R.; Drewery, John S.; Hill, Richard S.; Archer, Timothy M.; Kepten, Avishai, Selective electrochemical accelerator removal.
  33. Mayer, Steven T.; Rea, Mark L.; Hill, Richard S.; Kepten, Avishai; Stowell, R. Marshall; Webb, Eric G., Topography reduction and control by selective accelerator removal.
  34. Mayer, Steven T.; Rea, Mark L.; Hill, Richard S.; Kepten, Avishai; Stowell, R. Marshall; Webb, Eric G., Topography reduction and control by selective accelerator removal.
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