[특허]Method for low temperature bonding and bonded structure

Ziptronix, Inc.

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특허 상세정보

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내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Method for low temperature bonding and bonded structure

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/48
미국특허분류(USC)	438/455; 438/459; 438/974; 148/DIG.0012
출원번호	US-0505283 (2000-02-16)
발명자 / 주소	Tong, Qin-Yi Fountain, Jr., Gaius Gillman Enquist, Paul M.
출원인 / 주소	Ziptronix, Inc.
대리인 / 주소	Oblon, Spivak, McClelland, Maier &
인용정보	피인용 횟수 : 84 인용 특허 : 129

초록
▼

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process the method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughnes...

대표
청구항
▼

1. A bonding method, comprising:forming first and second silicon oxide materials; etching surfaces of said first and second silicon oxide materials using a plasma RIE process; exposing said silicon oxide materials to an ammonia-based solution after said etching; bringing together at room temperature said first and second silicon oxide materials after said etching and exposing steps; and forming a bond between said first and second silicon oxide materials. 2. A method as recited in claim 1, wherein said etching step comprises:etching said first and second silicon oxide materials such that respective surface roughnesses of said first and second silicon oxide materials after said etching are substantially the same as respective surface roughnesses before said etching. 3. A method as recited in claim 2, comprising:forming said first and second silicon oxide materials to each have a surface roughness in a range of 0.1 to 3.0 nm. 4. A method as recited in claim 1, comprising:allowing bonded groups to diffuse or dissociate away from an interface of said first and second silicon oxide materials. 5. A method as recited in claim 4, comprising:increasing bonding strength between said first and second silicon oxide materials by diffusing or dissociating away said bonding groups. 6. A method as recited in claim 1, comprising:after said etching step, immersing said first and second silicon oxide materials in an ammonia-based solution to form bonding surfaces terminated with a terminating species. 7. A method as recited in claim 6, wherein said species comprises an NH2 group.8. A method as recited in claim 1, comprising:exposing said first and second silicon oxide materials to one of an oxygen, argon, NH3 and CF4 plasma process. 9. A method as recited in claim 1, wherein forming at least one of said first and second silicon oxide materials comprises depositing a polishable material on a non-planar surface.10. A method as recited in claim 1, comprising:obtaining a bond of at least 500 mJ/m2 at room temperature. 11. A method as recited in claim 1, comprising:obtaining a bond of at least 1000 mJ/m2 at room temperature. 12. A method as recited in claim 1, comprising:obtaining a bond of at least 2000 mJ/m2 at room temperature. 13. A method as recited in claim 1, comprising:forming covalent bonds between said silicon oxide bonding materials. 14. A method as recited in claim 1, comprising:forming covalent bonds between said first and second silicon oxide materials in ambient. 15. A method as recited in claim 1, comprising:forming covalent bonds between said first and second silicon oxide materials in vacuum. 16. A method as recited in claim 1, comprising:forming a bond of sufficient energy to virtually eliminate wafer bowing after subsequent processing of said bonded first and second silicon oxide materials. 17. A method as recited in claim 16, comprising:forming a bond of sufficient energy to virtually eliminate wafer bowing after subsequent thermal cycling of said bonded first and second silicon oxide materials. 18. A method as recited in claim 1, comprising:increasing available bonding energy of bonding pairs on said first and second silicon oxide materials at approximately room temperature; and propagating said bonding at room temperature. 19. A method as recited in claim 18, comprising:propagating covalent bonding at room temperature. 20. A method as recited in claim 1, comprising:etching said first and second silicon oxide materials using an oxygen plasma. 21. A method as recited in claim 20, comprising:rinsing said first and second silicon oxide materials in an ammonia-based solution after said etching. 22. A method as recited in claim 21, comprising:rinsing said first and second materials in ammonium hydroxide after said etching. 23. A method as recited in claim 1, comprising:etching said first and second silicon oxide materials under vacuum; and bonding said first and second silicon oxide materials without breaking said vacuum. 24. A method as recited in claim 1, comprising:immersing said first and second silicon oxide materials into said ammonia-based solution after said etching. 25. A method as recited in claim 1, comprising:etching said first and second silicon oxide materials; forming a region having defects proximate to a surface of each of said first and second silicon oxide materials; and removing bonding by-products using said region. 26. A method as recited in claim 1, wherein said etching comprises:activating said first and second silicon oxide materials; and creating a region under surfaces of said first and second silicon oxide materials for removing bonding by-products. 27. A method as recited in claim 1, comprising:creating a region proximate to surfaces of said first and second silicon oxide materials for at least one of removal and conversion of bonding by-products to a species capable of being absorbed by or diffusing away from said surfaces. 28. A method as recited in claim 1, comprising:forming said first silicon oxide material by depositing an oxide layer on a first semiconductor wafer; forming said second silicon oxide material by depositing an oxide layer on a second semiconductor wafer; and bonding said first and second semiconductor wafers. 29. A method as recited in claim 1, comprising:forming said first silicon oxide material as a deposited oxide layer on a first semiconductor wafer, said first semiconductor wafer comprising a first substrate and a first active region; forming said second silicon oxide material as a deposited oxide layer on a second semiconductor wafer, said second semiconductor wafer comprising a second substrate and a second active region; bonding said first and second semiconductor wafers; and removing at least a substantial portion of one of said first and second substrates after said bonding. 30. A method as recited in claim 1, comprising:forming said first silicon oxide material as a deposited oxide layer on a semiconductor wafer, said semiconductor wafer comprising a substrate and an active region; forming said second silicon oxide material on a surrogate substrate; bonding said semiconductor wafer and said surrogate substrate; and removing at least a substantial portion of said first substrate after said bonding. 31. A method as recited in claim 1, wherein said bonding comprises:maintaining said first and second silicon oxide materials for a specified period in ambient. 32. A method as recited in claim 1, comprising:etching said first and second silicon oxide materials using a bonding fixture under vacuum; bonding said first and second silicon oxide materials using said fixture to bring together said first and second silicon oxide materials while maintaining said vacuum. 33. A method as recited in claim 1, comprising:forming a first silicon oxide layer on a first wafer containing electrical devices; and polishing said first silicon oxide layer to form said first silicon oxide material. 34. A method as recited in claim 33, comprising:forming a second silicon oxide layer on a second wafer containing electrical devices; and polishing said second silicon oxide layer to form said second silicon oxide material. 35. A method as recited in claim 34, comprising:forming said first silicon oxide layer on said first wafer containing electrical devices of a first technology; and forming said second silicon oxide layer on said second wafer containing electrical devices of a second technology different from said first technology. 36. A method as recited in claim 34, comprising:interconnecting one of said electrical devices on said first wafer and one of said electrical devices on said second wafer. 37. A method as recited in claim 34, comprising:forming said first silicon oxide material on a surface of a one of a thermal spreader, surrogate substrate, antenna, wiring layer, and pre-formed multi-layer interconnect. 38. A method as recited in claim 1, comprising:forming said first silicon oxide material on a first wafer containing a first integrated circuit. 39. A method as recited in claim 38, comprising:forming said second silicon oxide material on a second wafer containing a second integrated circuit. 40. A method as recited in claim 39, comprising:forming said first silicon oxide material on said first wafer containing said first integrated circuit of a first technology; and forming said second silicon oxide material on said second wafer containing said second integrated circuit of a second technology different from said first technology. 41. A method as recited in claim 39, comprising:interconnecting said first and second integrated circuits. 42. A method as recited in claim 1, comprising:said first and second silicon oxide materials being substantially planar. 43. A method as recited in claim 1, comprising:forming at least one of said first and second silicon oxide materials on a non-planar surface. 44. A method as recited in claim 1, comprising:forming surfaces of said first and second silicon oxide materials to be non-planar; and polishing said surfaces of said first and second silicon oxide materials. 45. A method as recited in claim 44, wherein:said polishing comprises chemical-mechanical polishing. 46. A method as recited in claim 1, comprising:obtaining etched surfaces using said etching step; and exposing said etched surfaces to a gaseous chemical environment to terminate said etched surfaces with a terminating species. 47. A method as recited in claim 1, comprising:forming a first silicon oxide layer on a first wafer containing electrical devices and having a non-planar surface; and forming a second silicon oxide layer on a second wafer containing electrical devices; and polishing said first and second silicon oxide layers. 48. A method as recited in claim 47, comprising:forming said second silicon oxide layer on said second wafer having a non-planar surface. 49. A method as recited in claim 1, comprising:forming a first silicon oxide layer on a first wafer containing electrical devices and having an irregular surface topology; and forming a second silicon oxide layer on a second wafer containing electrical devices; and polishing said first and second silicon oxide layers to form said first and second silicon oxide materials, respectively. 50. A method as recited in claim 49, comprising:forming said second silicon oxide layer on said second wafer having an irregular surface topology. 51. A method as recited in claim 1, wherein said first and second silicon oxide materials are formed on respective surfaces of first and second substrates, the method comprising:removing a substantial portion of one of said first and second substrates. 52. A method as recited in claim 51, wherein said first and second substrates have first and second electrical devices, the method comprising:interconnecting said first and second devices after said removing step. 53. A method as recited in claim 1, wherein said etching step comprises:etching said first and second silicon oxide materials such that respective surface roughnesses of said first and second silicon oxide materials after said etching is the same or less than respective surface roughnesses before said etching. 54. A method as recited in claim 1, comprising:activating surfaces of said first and second silicon oxide materials during said etching step; and separately from said etching step, terminating said surfaces with a terminating species. 55. A bonding method, comprising:forming first and second bonding surfaces each having a surface roughness in a range of 0.1 to 3 nm; removing material from said first and second bonding surfaces while maintaining said surface roughness; activating said first and second bonding surfaces by exposing said first and second bonding surfaces to an ammonia-based solution; and directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 500 mJ/m2. 56. A method as recited in claim 55, comprising:directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 1000 mJ/m2. 57. A method as recited in claim 55, comprising:directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 2000 mJ/m2. 58. A method as recited in claim 55, comprising:activating said first and second bonding surfaces and forming selected bonding groups on said first and second bonding surfaces. 59. A method as recited in claim 55, comprising:polishing respective first and second bonding surfaces to said surface roughness; and etching said first and second bonding surfaces after said polishing to activate said first and second bonding surfaces. 60. A method as recited in claim 55, comprising:converting bonding by-products to a species capable of being absorbed by or diffusing away from said bonding surfaces during said bonding step. 61. A method as recited in claim 55, comprising:etching said first and second bonding surfaces using a plasma RIE process; forming a subsurface layer having defects; and removing bonding by-products using said subsurface layer. 62. A method as recited in claim 55, comprising:forming said first bonding surface as a surface of a first semiconductor wafer having devices formed therein; and forming said second bonding surface as a surface of a second semiconductor wafer having devices formed therein. 63. A method as recited in claim 62, wherein one of said first and second wafers comprises a substrate, said method comprising:removing a substantial portion of said substrate. 64. A method as recited in claim 62, comprising:interconnecting devices in said first and second wafers. 65. A method as recited in claim 55, comprising:forming a first insulating layer on a first wafer containing electrical devices; polishing said first insulating layer to form said first bonding surface; forming a second insulating layer on a second wafer containing electrical devices; and polishing said second insulating layer to form said second bonding surface. 66. A method as recited in claim 55, comprising:forming a first insulating layer on a first wafer containing electrical devices and having an irregular surface topology; polishing said first insulating layer to form said first bonding surface; forming a second insulating layer on a second wafer containing electrical devices and having an irregular surface topology; and polishing said second insulating layer to form said second bonding surface. 67. A method as recited in claim 63, comprising:interconnecting devices in said first and second semiconductor wafers after said removing step. 68. A method as recited in claim 55, comprising:separately from said removing step, terminating said bonding surfaces with a terminating species. 69. A method as recited in claim 55, comprising:removing material from said bonding surfaces using a first gas; and terminating said bonding surfaces with a terminating species by exposing said bonding surfaces to a second gas different from said first gas. 70. A method as recited in claim 55, comprising:immersing said first and second bonding surfaces in an ammonia-based solution. 71. A method as recited in claim 55, comprising:immersing said first and second bonding surfaces in an ammonium hydroxide solution. 72. A method as recited in claim 55, comprising:directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 1000 mJ/m2 within 24 hours. 73. A bonding method, comprising:forming first and second bonding surfaces; etching said first and second bonding surfaces; terminating said first and second bonding surfaces with a species allowing formation of chemical bonds at about room temperature; and forming chemical bonds between said first and second bonding surfaces at about room temperature. 74. A method as recited in claim 73, comprising:bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 500 mJ/m2. 75. A method as recited in claim 73, comprising:bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 1000 mJ/m2. 76. A method as recited in claim 73, comprising:bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 2000 mJ/m2. 77. A method as recited in claim 73, comprising:activating said first and second bonding surfaces prior to said bonding step. 78. A method as recited in claim 73, comprising:polishing said first and second bonding surfaces; and etching said first and second bonding surfaces after said polishing to activate said first and second bonding surfaces. 79. A method as recited in claim 73, comprising:converting bonding by-products to a species capable of being absorbed by or diffusing away from said bonding surfaces during said bonding step. 80. A method as recited in claim 73, comprising:forming said first bonding surface as a surface of a first semiconductor wafer having devices formed therein; and forming said second bonding surface as a surface of a second semiconductor wafer having devices formed therein. 81. A method as recited in claim 80, wherein one of said first and second wafers comprises a substrate, said method comprising:removing a substantial portion of said substrate. 82. A method as recited in claim 80, comprising:interconnecting devices in said first and second wafers. 83. A method as recited in claim 73, comprising:forming a first insulating layer on a first wafer containing electrical devices; polishing said first insulating layer to form said first bonding surface; forming a second insulating layer on a second wafer containing electrical devices; and polishing said second insulating layer to form said second bonding surface. 84. A method as recited in claim 73, comprising:forming a first insulating layer on a first wafer containing electrical devices and having an irregular surface topology; polishing said first insulating layer to form said first bonding surface; forming a second insulating layer on a second wafer containing electrical devices and having an irregular surface topology; and polishing said second insulating layer to form said second bonding surface. 85. A method as recited in claim 73, comprising:activating said bonding surfaces during said etching step; and separately from said etching step, terminating said bonding surfaces with said species. 86. A method as recited in claim 73, comprising:etching said bonding surfaces using a first gas; and terminating said bonding surfaces with a terminating species by exposing said bonding surfaces to a second gas different from said first gas. 87. A method as recited in claim 73, comprising:activating said first and second bonding surfaces by exposing said first and second bonding surfaces to an ammonia-based solution. 88. A method as recited in claim 73, comprising:immersing said first and second bonding surfaces in an ammonia-based solution. 89. A method as recited in claim 73, comprising:immersing said first and second bonding surfaces in an ammonium hydroxide solution. 90. A method as recited in claim 73, comprising:directly bonding said first and second bonding surfaces at room temperature with a bonding strength of at least 1000 mJ/m2 within 24 hours. 91. A bonding method, comprising:forming first and second bonding surfaces; planarizing said first and second bonding surfaces; etching said first and second bonding surfaces after planarizing; bringing into direct contact said first and second bonding surfaces after said etching step; and forming a chemical bond near room temperature between said first and second bonding surfaces. 92. A method as recited in claim 91, wherein:forming said first and second bonding surfaces comprises forming first and second bonding layers on respective first and second substrates; said method comprising removing a substantial portion of one of said first and second substrates after said bonding. 93. A method as recited in claim 92, comprising:depositing a silicon oxide layer as each of said first and second bonding layers. 94. A method as recited in claim 91, wherein:forming said first bonding surface comprises depositing a first silicon oxide layer on a first substrate; forming said second bonding surface comprises depositing a second silicon oxide layer on a second substrate; and etching comprises etching said first and second bonding surfaces using a plasma. 95. A method as recited in claim 91, wherein:said planarizing comprises polishing said first and second bonding surfaces. 96. A method as recited in claim 95, comprising:polishing said first and second surfaces to a roughness in the range of 0.1 to 3 nm. 97. A method as recited in claim 96, wherein:a surface roughness of said first and second bonding surfaces after said etching is in the range of 0.1 to 3 nm. 98. A method as recited in claim 91, wherein:planarizing comprises polishing said first and second bonding surfaces each to a surface roughness; and after said etching said first and second bonding surfaces each have approximately said surface roughness. 99. A method as recited in claim 91, comprising:after said etching step, immersing said first and second bonding surfaces in one of NH4OH, NH4F and HF. 100. A method as recited in claim 91, comprising:performing a second etching process after said etching step. 101. A method as recited in claim 91, comprising:forming said chemical bond to a strength of at least 500 mJ/cm2. 102. A method as recited in claim 91, comprising:forming said chemical bond to a strength of at least 1000 mJ/cm2. 103. A method as recited in claim 91, comprising:forming said chemical bond to a strength of at least 2000 mJ/cm2. 104. A method as recited in claim 91, comprising:forming a covalent bond near room temperature between said first and second bonding surfaces. 105. A method of bonding workpieces, comprising:depositing first and second bonding layers on respective first and second workpieces; planarizing said first and second bonding layers; etching said first and second bonding layers after planarizing to activate respective first and second surfaces of said first and second bonding layers; terminating said first and second surfaces with a terminating chemical species after etching; bringing into direct contact said first and second surfaces after said etching step; and forming a chemical bond between said first and second workpieces at room temperature. 106. A method as recited in claim 105, wherein:depositing each of said first and second bonding layers comprises depositing a silicon oxide layer; planarizing comprises polishing said first and second bonding layers; etching comprises exposing said first and second bonding layers to a plasma; and terminating comprises immersing said first and second bonding surfaces in an ammonia-based solution. 107. A method as recited in claim 105, wherein:said first and second workpieces each comprises a semiconductor wafer having one of devices and connections. 108. A method as recited in claim 105, wherein:said first workpiece comprises a semiconductor wafer having one of devices and connections; and said second workpiece comprises one of a circuit substrate, a packaging material and a surrogate substrate. 109. A bonding method, comprising:forming first and second layers of silicon oxide material on respective first and second elements; polishing said first and second layers of silicon oxide to a surface roughness of no more than about 0.1 to 3 nm; etching said first and second layers, after said polishing step, by exposing said layers to a plasma reactive ion etch process; bringing into contact said first and second layers in ambient at room temperature, after said etching step; and forming a chemical bond between said first and second layers at room temperature. 110. A method as recited in claim 109, comprising:etching said first and second layers using one of oxygen, CF4, and Ar plasma reactive ion etch process. 111. A method as recited in claim 109, comprising:rinsing said first and second layers in an ammonia-based solution after said etching to terminate said layers with a terminating species. 112. A method as recited in claim 109, wherein said etching step comprises:etching said first and second layers such that respective surface roughnesses of said first and second layers after said etching is the same or less than respective surface roughnesses before said etching. 113. A method as recited in claim 109, comprising:a surface roughness of each of said first and second layers after said etching step is in the range of 0.1 to 3 nm. 114. A method as recited in claim 109, comprising:after bonding, maintaining said first and second layers at room temperature; and forming a chemical bond having a strength of at least 500 mJ/m2 within 24 hours. 115. A method as recited in claim 109, comprising:after bonding, maintaining said first and second layers at room temperature; and forming a chemical bond having a strength of at least 1000 mJ/m2 within 24 hours. 116. A method as recited in claim 109, comprising:etching said surfaces at a rate of about 0.5 to 2 Å per minute. 117. A method as recited in claim 109, comprising:terminating said layers with a terminating species. 118. A method as recited in claim 117, wherein said terminating comprises exposing said layers to a solution.119. A method as recited in claim 117, wherein said terminating comprises exposing said layers to a gas.120. A method as recited in claim 117, comprising:terminating at least one of said layers, wherein said terminating comprises one of using a solution, plasma exposure and exposure to a gas. 121. A method as recited in claim 117, comprising:terminating said layers by forming at least a monolayer of one of an atom and a molecule. 122. A method as recited in claim 117, comprising:terminating said layers by forming at least a few monolayers of one of an atom and a molecule. 123. A method as recited in claim 117, comprising:terminating said layers with one of a silanol group, a fluorine group, an NH2 group and an HF group. 124. A method as recited in claim 109, comprising:forming said chemical bond using a chemical reaction with byproducts of said bonding step. 125. A method as recited in claim 124, wherein said byproducts are bonding groups.126. A method as recited in claim 124, comprising:diffusing said byproducts away from an interface between said bonding layers. 127. A method as recited in claim 126, wherein said diffusing increases a bond strength.128. A method as recited in claim 109, comprising:after said bringing step, maintaining said first and second layers at said room temperature and forming a bond of a strength of at least 500 mJ/m2. 129. A method as recited in claim 109, comprising:after said bringing step, maintaining said first and second layers at said room temperature and forming a bond of a strength of at least 1000 mJ/m2. 130. A method as recited in claim 109, wherein said etching comprises terminating said first and second bonding layers with a terminating species.131. A method as recited in claim 130, comprising:terminating said layers with one of a silanol group, a fluorine group, an NH2 group and an HF group. 132. A method as recited in claim 130, comprising:terminating said layers by forming at least a monolayer of one of an atom and a molecule. 133. A method as recited in claim 130, comprising:terminating said layers by forming at least a few monolayers of one of an atom and a molecule. 134. A bonding method, comprising:forming first and second silicon oxide bonding materials; etching said first and second silicon oxide bonding materials using plasma reactive ion etching with a first gas; separate from said etching, terminating said silicon oxide bonding materials with a terminating species; bringing together, at room temperature in ambient, said first and second silicon oxide bonding materials after said etching and terminating steps; and forming a chemical bond between said first and second silicon oxide bonding materials at room temperature. 135. A method as recited in claim 134, wherein said etching step comprises:etching said first and second silicon oxide bonding materials such that respective surface roughnesses of said first and second silicon oxide bonding materials after said etching is the same or less than respective surface roughnesses before said etching. 136. A method as recited in claim 134, comprising:a surface roughness of each of said first and second silicon oxide bonding materials before and after said etching step is in the range of 0.1 to 3 nm. 137. A method as recited in claim 134, comprising:after bonding, maintaining said first and second silicon oxide bonding materials at room temperature; and forming a chemical bond having a strength of at least 500 mJ/m2 within 24 hours. 138. A method as recited in claim 134, comprising:after bonding, maintaining said first and second silicon oxide bonding materials at room temperature; and forming a chemical bond having a strength of at least 1000 mJ/m2 within 24 hours. 139. A method as recited in claim 134, comprising:etching said first and second silicon oxide bonding materials at a rate of about 0.5 to 2 Å per minute. 140. A method as recited in claim 134, comprising:terminating said silicon oxide bonding materials by exposing said silicon oxide bonding materials to a second gas different from said first gas. 141. A bonding method, comprising:forming first and second silicon oxide layers; etching surfaces of said first and second silicon oxide layers using a plasma reactive ion etch process; exposing said silicon oxide layers to an ammonia-based solution after said etching; bringing together at room temperature said surfaces of said first and second silicon oxide layers after said etching and exposing steps; and forming a chemical bond between said first and second silicon oxide layers at room temperature. 142. A method as recited in claim 141, where said exposing step comprises:exposing said first and second silicon oxide layers to ammonium hydroxide. 143. A method as recited in claim 141, where said exposing step comprises:immersing said first and second silicon oxide layers in an ammonium hydroxide solution. 144. A method as recited in claim 141, comprising:forming a covalent bond between said first and second silicon oxide layers at room temperature. 145. A method as recited in claim 141, comprising:etching surfaces of said first and second silicon oxide layers using an Ar plasma reactive ion etch process. 146. A method as recited in claim 141, comprising:forming a chemical bond between said first and second silicon oxide layers at room temperature with a bonding strength of at least 1000 mJ/m2 within 24 hours. 147. A method as recited in claim 141, comprising:removing material from said first and second silicon oxide layers.

이 특허에 인용된 특허 (129)

이 특허를 인용한 특허 피인용횟수: 84

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구성항목	관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
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Method for low temperature bonding and bonded structure

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Method for low temperature bonding and bonded structure

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대표청구항 ▼

이 특허에 인용된 특허 (129)

이 특허를 인용한 특허 피인용횟수: 84

IPC 상위 출원인

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IPC 상세정보(version : 201201)

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