IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0774553
(2001-01-31)
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발명자
/ 주소 |
- Staver, Daniel Arthur
- Van Stralen, Nick Andrew
- Wodnicki, Robert Gideon
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출원인 / 주소 |
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인용정보 |
피인용 횟수 :
23 인용 특허 :
8 |
초록
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A real time imaging system includes a programmable detector framing node controlling generation of radiation and controlling radioscopic image detection. Radioscopic image data is acquired and communicated by the detector framing node independently of a host computer operating system. The detector f
A real time imaging system includes a programmable detector framing node controlling generation of radiation and controlling radioscopic image detection. Radioscopic image data is acquired and communicated by the detector framing node independently of a host computer operating system. The detector framing node controls events in real time according to an event instruction sequence and communicates the received radioscopic image data to host memory through a computer communication bus. The image data is received from a selected flat panel detector of a plurality of different flat panel detectors. The detector framing node is programmable by way of a pair of JTAG loops. The JTAG loops receive programming instructions from the host computer and from a pair of JTAG ports.
대표청구항
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1. A programmable image data acquisition system, comprising:a host computer having at least one host processor to execute operations with a host operating system and a host memory to store image data; and a programmable detector framing node to receive image data output from an image detection syste
1. A programmable image data acquisition system, comprising:a host computer having at least one host processor to execute operations with a host operating system and a host memory to store image data; and a programmable detector framing node to receive image data output from an image detection system and communicate the received image data to the host memory, said detector framing node being selectably programmable by reading a programmable memory unit after power is initially applied thereto. 2. The system according to claim 1, said detector framing node further comprising:a plurality of frame buffer memory units to store the received image data output from the image detection system; and a control unit comprising the programmable memory unit, a data acquisition processor to control storage and retrieval of the image data in the frame buffer memory units, and an event processor to execute event instructions to control the detector framing node and the image detection system. 3. The system according to claim 2, said detector framing node further comprising:a JTAG port being connected to the programmable memory unit through a JTAG loop, such that instructions for programming the programmable memory unit are communicable to the programmable memory unit by way of the JTAG port. 4. The system according to claim 3, said detector framing node further comprising:a computer communication interface for connecting said detector framing node to said host computer by way of a computer communication bus; and a local bus connecting the computer communication interface to the control unit, wherein the JTAG loop is selectably connectable to the local bus such that the programmable memory unit is programmed by way of instructions communicated by the at least one host processor over the computer communication bus, through the computer communication interface, to the local bus, and over the JTAG loop. 5. The system according to claim 2, said detector framing node communicating with the at least one host processor over the computer communication bus at a first clock frequency and receiving the image data from the image detection system at a second clock frequency different from the first clock frequency.6. The system according to claim 5, said detector framing node communicating with the at least one host processor over the computer communication bus in parallel at the first clock frequency and receiving the image data from the image detection system in serial at the second clock frequency.7. The system according to claim 5, wherein the first clock frequency is a PCI frequency of at least 33 MHz and the second clock frequency is a fiber optic transmission clock frequency of at least 1 GHz.8. The system according to claim 2, wherein the event processor controls communication of event instructions to a radiation generation system for controlling generation of radiation.9. The system according to claim 2, wherein the received image data is radioscopic image data, and the image detection system is an x-ray detection system.10. The system according to claim 2, wherein the programmable memory unit is comprised of a plurality of daisy chained eeproms.11. The system according to claim 10, wherein the plurality of daisy chained eeproms are selectably connected to said host computer by way of at least one JTAG loop communicating with a computer communication bus by way of a computer communication interface.12. The system according to claim 10, wherein each of the event processor and the data acquisition processor has an associated eeprom unit, which is respectively programmable in a passive serial mode.13. The system according to claim 1, said detector framing node further comprising:a power on reset unit to delay application of power for booting the programmable memory unit for a predetermined time period after power is applied to said detector framing node. 14. The system according to claim 13, wherein the predetermined period of time is at least 140 msec.15. The system according to claim 1, said detector framing node further comprising:a JTAG port being connected to the programmable memory unit through a JTAG loop, such that instructions for programming the programmable memory unit are communicable to the programmable memory unit by way of the JTAG port. 16. The system according to claim 1, further comprising:a computer communication interface connecting said detector framing node to said host computer by way of a computer communication bus; and a local bus connecting the computer communication interface to the control unit, wherein a JTAG loop communicates with the local bus such that the programmable memory unit is programmed by way of instructions communicated by the at least one host processor over the computer communication bus, through the computer communication interface, to the local bus, and over the JTAG loop. 17. The system according to claim 1, wherein the host computer operating system is a non-real time operating system.18. The system according to claim 1, wherein the host computer operating system is a real time operating system.19. The system according to claim 1, wherein the host computer operating system is a task based operating system.20. The system according to claim 1, wherein the received image data is received in real time from the image detection system.21. The system according to claim 1, said detector framing node further comprising:a first JTAG port being connected to the programmable memory unit through a first JTAG loop, such that instructions for programming the programmable memory unit are communicable to the programmable memory unit by way of the first JTAG port; and a second JTAG port being connected to said control unit by way of a second JTAG loop, such that instructions may be communicated to the control unit independent of communication with the programmable memory unit. 22. The system according to claim 1, said detector framing node further comprising:a computer communication interface connecting said detector framing node to said host computer by way of a computer communication bus; and a local bus connecting the computer communication interface to the control unit, wherein a first JTAG loop communicates with the local bus such that the programmable memory unit is programmed by way of instructions communicated by the at least one host processor over the computer communication bus, through the computer communication interface, to the local bus, and over the JTAG loop, and wherein a second JTAG loop communicates with said control unit such that instructions may be communicated independent of communication with the programmable memory unit. 23. The system according to claim 1,said detector framing node further comprising a control unit comprising the programmable memory unit, a data acquisition processor to control storage and retrieval of the image data in a plurality of frame buffer memory units, and an event processor to execute event instructions to control the detector framing node and the image detection system, the system comprising an event processor power on reset unit to delay application of power to the event processor and a data acquisition processor power on reset unit to delay application of power to the data acquisition processor. 24. The system according to claim 1, said detector framing node further comprising:an image detection interface to receive the image data from an image detection system; and a memory unit to store the image data received by said image detection interface before communication to the host memory. 25. The system according to claim 24, wherein the image detection interface is a fiber optic interface to receive the image data over an optical fiber data link.
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