초록

A system and method for allowing simultaneous access to different sections of a memory utilizes a memory including a number of memory banks which may be divided among several partitions. Control circuitry allows simultaneous access to memory banks from each partition.

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1. A memory comprising:a set of memory banks; a set of controllers, each controller associated with a memory bank and providing access to the associated memory bank, each of the controllers including circuitry to determine whether or not an associated memory bank is active within a clock cycle; and

1. A memory comprising:a set of memory banks; a set of controllers, each controller associated with a memory bank and providing access to the associated memory bank, each of the controllers including circuitry to determine whether or not an associated memory bank is active within a clock cycle; and a register storing partition information; wherein the set of memory banks is selectively partitionable into a first partition and a second partition; and wherein during each clock cycle at least one memory bank from each set may exchange data with its associated controller. 2. The memory of claim 1 comprising DRAM memory cells.3. The memory of claim 1 comprising SRAM memory cells.4. A method of accessing a memory, the memory comprising a plurality of memory banks, each memory bank including at least a controller to determine whether or not an associated memory bank is active within a clock cycle, the method comprising partitioning the memory banks according to a configuration register and on each clock cycle, accessing a plurality of memory banks and exchanging data between the plurality of memory banks and a set of external data lines.5. The method of claim 4, comprising accepting signals from a first set of address and control lines and from a second set of address and control lines, wherein during each clock cycle the signals are sent to a subset of the memory banks.6. The method of claim 4 wherein the plurality of memory banks are divided into partitions, wherein on each clock cycle at least one memory bank per partition may be accessed.7. The memory of claim 4, wherein the memory banks are partitioned into a code partition and a data partition.8. The method of claim 4 comprising accepting signals from a first set of address and control lines and from a second set of address and control lines, wherein during each clock cycle the signals are sent to a subset of the memory banks.9. The method of claim 4 wherein the plurality of memory banks are divided into partitions, wherein on each clock cycle at least one memory bank per partition may be accessed.