Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/44
H01L-021/30
H01L-021/46
출원번호
US-0113148
(2002-03-28)
발명자
/ 주소
Swan, Johanna M.
Mahajan, Ravi V.
Natarajan, Bala
출원인 / 주소
Intel Corporation
대리인 / 주소
Blakely, Sokoloff, Taylor &
인용정보
피인용 횟수 :
14인용 특허 :
90
초록▼
The opening is initially fabricated in an upper surface of a wafer substrate, which allows for the use of alignment features on the upper surface of the wafer substrate. The openings are then filled with plugs. An integrated circuit is then manufactured over the upper surface of the substrate and th
The opening is initially fabricated in an upper surface of a wafer substrate, which allows for the use of alignment features on the upper surface of the wafer substrate. The openings are then filled with plugs. An integrated circuit is then manufactured over the upper surface of the substrate and the plugs. The plugs are located below the integrated circuit and do not take up “real estate” reserved for metal layers of the integrated circuit. A carrier is then bonded to an upper surface of the integrated circuit, whereafter a lower portion of the wafer substrate is removed in a grinding and etching operation. The plugs are then removed through a lower surface of the wafer substrate, whereafter the openings are filled with conductive members in a plating operation. A metal redistribution layer can be formed on a lower surface of the wafer substrate, because the carrier provides sufficient rigidity.
대표청구항▼
1. A method of constructing art electronic assembly, comprising:forming a plurality of plugs in a first substrate; manufacturing a first integrated circuit on a first side of the first substrate, the first substrate and the first integrated circuit jointly forming a first die; removing the plugs to
1. A method of constructing art electronic assembly, comprising:forming a plurality of plugs in a first substrate; manufacturing a first integrated circuit on a first side of the first substrate, the first substrate and the first integrated circuit jointly forming a first die; removing the plugs to leave a plurality of openings in the first substrate; forming a seed layer in each opening and as a contact on a second side of the first substrate opposing the first side; plating a plurality of conductive members, each conductive member having a respective portion being plated on a portion of the seed layer in the respective opening to form a via in each respective opening and being plated on a contact of the respective seed layer on the second side of the first substrate to form a bump on each respective contact and standing proud of the substrate; and locating the first die on a second component having a circuit, the first integrated circuit being connected through the material of the bump and the via of each conductive members to the circuit of the second component. 2. The method of claim 1, wherein the plugs are formed in a first surface of the first substrate and the first integrated circuit is manufactured on the first surface.3. The method of claim 2, further comprising:removing a sacrificial portion of the first substrate opposing the first surface to leave the first substrate with a second surface opposing the first surface, the plugs being exposed by said removal and being removed through the second surface. 4. The method of claim 3, further comprising:bonding a side of the first die opposing the sacrificial portion that is removed to a carrier, the sacrificial portion being removed while the first die is bonded to the carrier. 5. The method of claim 4, wherein at least some of the sacrificial portion is removed in a grinding operation.6. The method of claim 5, wherein some of the sacrificial portion is etched away.7. The method of claim 3, further comprising:mounting the first die to a mount structure with the first die between the mount structure and the carrier; and removing the carrier from the die after the die is mounted to the mount structure. 8. The method of claim 7, wherein the first die is part of a processed wafer, further comprising:singulating the first die from the wafer substrate after the carrier is removed. 9. The method of claim 8, further comprising:removing the die from the mount structure after the first die is singulated from the wafer. 10. The method of claim 1, wherein the conductive members are plated in the openings.11. The method of claim 10, further comprising:depositing an oxide layer in each opening, the conductive members being formed over the oxide layers. 12. The method of claim 11,wherein the seed layer is deposited on each oxide layer. 13. The method of claim 1, wherein the second component has a second substrate and the circuit of the second component is a second integrated circuit formed on the second substrate.14. The method of claim 13, further comprising:forming a plurality of plugs in the second substrate; removing the plugs from the second substrate; and forming a conductive member in each opening in the second substrate. 15. The method of claim 1, wherein the conductive members are in at least a 3×3 array.16. The method of claim 1, wherein each conductive member is located on a respective terminal of the second die.17. The method of claim 1, wherein at least metallization layers of the first integrated circuit are manufactured after the plugs are formed.18. The method of claim 17, wherein the plugs are removed after at least transistors of the first integrated circuit are manufactured.19. A method of constructing an electronic assembly, comprising:forming a plurality of plugs in a first surface of a first substrate; manufacturing a first integrated circuit on the first surface of the first substrate, the first substrate and the first integrated circuit jointly forming a first die; removing a sacrificial portion of the first substrate opposing the first surface to leave the first substrate with a second surface opposing the first surface exposed by said removal; removing the plugs through the second surface to leave a plurality of openings in the first substrate; forming a conductive member in each opening; and locating the first die on a second component having a circuit, the first integrated circuit being connected through the conductive members to the circuit of the second component. 20. The method of claim 19, further comprising:bonding a side of the first die opposing the sacrificial portion that is removed to a carrier, the sacrificial portion being removed while the first die is bonded to the carrier. 21. The method of claim 20, wherein at least some of the sacrificial portion is removed in a grinding operation.22. The method of claim 21, wherein some of the sacrificial portion is etched away.23. The method of claim 19, further comprising:mounting the first die to a mount structure with the first die between the mount structure and the carrier; and removing the carrier from the die after the die is mounted to the mount structure. 24. The method of claim 23, wherein the first die is part of a processed wafer, further comprising:singulating the first die from the wafer substrate after the carrier is removed. 25. The method of claim 24, further comprising:removing the die from the mount structure after the first die is singulated from the wafer. 26. The method of claim 19, wherein the conductive members are plated in the openings.27. The method of claim 26, further comprising:depositing an oxide layer in each opening, the conductive members being formed over the oxide layers. 28. The method of claim 27, further comprising:depositing a metal layer on each oxide layer, the conductive members being plated on the metal layer. 29. The method of claim 19, wherein the second component has a second substrate and the circuit of the second component is a second integrated circuit formed on the second substrate.30. The method of claim 29, further comprising:forming a plurality of plugs in the second substrate; removing the plugs from the second substrate; and forming a conductive member in each opening in the second substrate. 31. The method of claim 19, wherein the conductive members are in at least a 3×3 array.32. The method of claim 19, wherein each conductive member is located on a respective terminal of the second die.33. The method of claim 32, wherein at least metallization layers of the first integrated circuit are manufactured after the plugs are formed.34. The method of claim 32, wherein the plugs are removed after at least transistors of the first integrated circuit are manufactured.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (90)
Anthony Thomas R. (Schenectady NY), Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers.
Donald O. Anstrom ; Bruce J. Chamberlin ; James W. Fuller, Jr. ; John M. Lauffer ; Voya R. Markovich ; Douglas O. Powell ; Joseph P. Resavy ; James R. Stack, Conductive substructures of a multilayered laminate.
Bertin Claude L. (South Burlington VT) Cronin John E. (Milton VT) Perlman David J. (Wappingers Falls NY), Cube wireability enhancement with chip-to-chip alignment and thickness control.
Beilstein ; Jr. Kenneth E. (Essex Junction VT) Bertin Claude L. (So. Burlington VT) Cronin John E. (Milton VT) Howell Wayne J. (Williston VT) Leas James M. (So. Burlington VT) Phillips Robert B. (Sta, Electronic modules with interconnected surface metallization layers.
Beilstein ; Jr. Kenneth E. (Essex Junction VT) Bertin Claude L. (So. Burlington VT) Cronin John E. (Milton VT) Howell Wayne J. (Williston VT) Leas James M. (So. Burlington VT) Phillips Robert B. (Sta, Electronic modules with interconnected surface metallization layers and fabrication methods therefore.
Beilstein ; Jr. Kenneth E. (Essex Junction VT) Bertin Claude L. (South Burlington VT) Howell Wayne J. (South Burlington VT), Fabrication processes for monolithic electronic modules.
Haj-Ali-Ahmadi Javad (Austin TX) Farrar Paul A. (South Burlington VT) Frankeny Jerome A. (Taylor TX) Frankeny Richard F. (Austin TX) Hermann Karl (Romulus NY) Shorter-Beauchamp Jacqueline A. (Austin , High density memory module.
Bertin Claude L. (South Burlington VT) Howell Wayne J. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT), Integrated memory cube structure.
Bertin Claude L. (South Burlington VT) Howell Wayne J. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT), Integrated memory cube, structure and fabrication.
Bertin Claude L. (South Burlington VT) Howell Wayne J. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Kalter Howard K. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT), Integrated multichip memory module structure.
Hinrichsmeyer Kurt (Sindelfingen DEX) Straehle Werner (Dettenhausen VT DEX) Kelley ; Jr. Gordon A. (Essex Junction VT) Noth Richard W. (Fairfax VT), Integrated semiconductor chip package.
Bertin Claude L. (Burlington VT) Miller Christopher P. (Underhill VT) Perlman David J. (Wappingers Falls NY), Intra-module spare routing for high density electronic packages.
Bertin Claude L. (So. Burlington VT) Farrar Paul A. (So. Burlington VT) Kelley ; Jr. Gordon A. (Essex Junction VT) Miller Christopher P. (Underhill VT), Method and apparatus for a stress relieved electronic module.
Beilstein ; Jr. Kenneth E. (Essex Junction VT) Bertin Claude L. (South Burlington VT) Cronin John E. (Milton VT) Howell Wayne J. (Williston VT) Leas James M. (South Burlington VT) Perlman David J. (W, Method and workpiece for connecting a thin layer to a monolithic electronic module\s surface and associated module packa.
Doo ; Ven Y. ; Nichols ; Donald R. ; Silvey ; Gene A., Method for depositing continuous pinhole free silicon nitride films and products produced thereby.
Lakritz, Mark N.; Ordonez, Jose; Tubiola, Peter J., Method for forming elongated solder connections between a semiconductor device and a supporting substrate.
Lehmann Volker (Munich DEX) Willer Josef (Riemerling DEX) Hoenlein Wolfgang (Unterhaching DEX), Method for manufacturing a solar cell from a substrate wafer.
Hua Chang-Hwang (Palo Alto CA) Chan Simon S. (Belmont CA) Day Ding-Yuan S. (Sunnyvale CA) Lee Adrian C. (Fremont CA), Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips.
Bertin Claude L. (South Burlington VT) Howell Wayne J. (Williston VT) Kalter Howard L. (Colchester VT), Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack.
Bhatt Anilkumar C. (Johnson City NY) Magnuson Roy H. (Endicott NY) Markovich Voya R. (Endwell NY) Papathomas Konstantinos I. (Endicott NY) Powell Douglas O. (Endicott NY), Method of preparing a printed circuit board.
Hua Chang-Hwang (Palo Alto CA) Day Ding-Yuan S. (Sunnyvale CA) Chan Simon S. (Belmont CA), Method of selective via-hole and heat sink plating using a metal mask.
Hynecek Jaroslav (Bedford OH) Ko Wen H. (Cleveland Heights OH) Yon Eugene T. (Lyndhurst OH), Miniature pressure transducer for medical use and assembly method.
Beilstein ; Jr. Kenneth E. (Essex Center VT) Bertin Claude L. (South Burlington VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT) Miller Christopher P. (Underhill VT) Po, Multichip integrated circuit packages and systems.
Bertin Claude L. (South Burlington VT) Farrar ; Sr. Paul A. (South Burlington VT) Howell Wayne J. (South Burlington VT) Miller Christopher P. (Underhill VT) Perlman David J. (Wappingers Falls NY), Polyimide-insulated cube package of stacked semiconductor device chips.
Bertin Claude L. (South Burlington VT) Cronin John E. (Milton VT) Perlman David J. (Wappingers Falls NY), Process for aligning etch masks on an integrated circuit surface using electromagnetic energy.
Bansal Jai P. (Manassas VA) Bertin Claude L. (S. Burlington VT) Troutman Ronald R. (Essex Junction VT), Process for fabrication of stacked, complementary MOS field effect transistor circuits.
Swanson Alan W. (Marlboro MA) Snider Charles R. (Southborough MA) Spooner Frank H. (Concord MA), Selective epitaxial etch planar processing for gallium arsenide semiconductors.
Spooner Frank H. (Concord MA) Snider Charles R. (Southboro MA) Heaton John L. (Bedford MA), Selective epitaxial growth of gallium arsenide with selective orientation.
Beilstein ; Jr. Kenneth E. (Essex Junction VT) Bertin Claude L. (Burlington VT) Daubenspeck Timothy H. (Colchester VT) Howell Wayne J. (Williston VT), Semiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module.
Bertin Claude L. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Howell Wayne J. (South Burlington VT), Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit.
Beilstein ; Jr. Kenneth E. (Essex Junction VT) Bertin Claude L. (South Burlington VT) Kelley ; Jr. Gordon A. (Essex Junction VT) Miller Christopher P. (Underhill VT), Thermally enhanced semiconductor chip package.
Bertin Claude L. (South Burlington VT) Farrar ; Sr. Paul A. (South Burlington VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT) van der Hoeven Willem B. (Jericho VT) Whi, Three dimensional multichip package methods of fabrication.
Pricer Wilber D. (Burlington VT) Faure Thomas B. (Milton VT) Meyerson Bernard S. (Yorktown Heights NY) Nestork William J. (Hinesburg VT) Turnbull ; Jr. John R. (Shelburne VT), Three-dimensional semiconductor structures formed from planar layers.
Black James F. (Newington CT) Grudkowski Thomas W. (Glastonbury CT) DeMaria Anthony J. (West Hartford CT), Ultra-thin microelectronic pressure sensors.
Muthukumar, Sriram; Mancera, Raul; Tomita, Yoshihiro; Hwang, Chi-won, Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias.
Huang, Min Lung; Wang, Wei Chung; Cheng, Po Jen; Yee, Kuo Chung; Su, Ching Huei; Lo, Jian Wen; Lin, Chian Chi, Three-dimensional package and method of making the same.
Huang, Min-Lung; Wang, Wei-Chung; Cheng, Po-Jen; Yee, Kuo-Chung; Su, Ching-Huei; Lo, Jian-Wen; Lin, Chian-Chi, Three-dimensional package and method of making the same.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.