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Instruction processor and programmable logic device cooperative computing arrangement and method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0930607 (2001-08-15)
발명자 / 주소
  • Stamm, Reto
  • McGloin, Ciaran
  • McNicholl, David
출원인 / 주소
  • Xilinx, Inc.
인용정보 피인용 횟수 : 24  인용 특허 : 13

초록

A method and arrangement for executing instructions of a computer program using a programmable logic device to perform selected functions of the program. Profile data for code segments of the computer program are generated during program execution. Based on the profile data, a code segment is select

대표청구항

1. A method for executing instructions of a computer program in a computing arrangement that includes an instruction processing engine coupled to a programmable logic device (PLD), comprising the steps of:profiling the computer program during execution on the instruction processing engine, whereby p

이 특허에 인용된 특허 (13)

  1. Sample Stephen P. (Mountain View CA) D\Amour Michael R. (Los Altos Hills CA) Payne Thomas S. (Union City CA), Apparatus for emulation of electronic hardware system.
  2. Greenbaum Jack E. ; Baxter Michael A., Compiling system and method for partially reconfigurable computing.
  3. Casselman Steven M., Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed.
  4. Casselman Steven M., Computer with programmable arrays which are reconfigurable in response to instructions to be executed.
  5. Guccione Steven A. ; Levi Delon, Configuration of programmable logic devices with routing core generators.
  6. Casselman Steven Mark (Reseda CA), FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in.
  7. Delon Levi ; Steven A. Guccione, Method and apparatus for evolving configuration bitstreams.
  8. Mason Martin T. ; Evans Scott C. ; Aranake Sandeep S., Method and system for configuring an array of logic devices.
  9. Knapp Steven K. (Santa Clara CA) Seidel Jorge P. (San Jose CA) Kelem Steven H. (Los Altos Hills CA), Method for generating logic modules from a high level block diagram.
  10. Guccione Steven A., Method of designing FPGAs for dynamically reconfigurable computing.
  11. Austin H. Lesea ; Stephen M. Trimberger, Supporting multiple FPGA configuration modes using dedicated on-chip processor.
  12. Bernardo Elayda, System and method for configuring a programmable logic device.
  13. Casselman Steven, Virtual computer of plural FPG's successively reconfigured in response to a succession of inputs.

이 특허를 인용한 특허 (24)

  1. Pritchard, J. Orion, Allocating hardware resources for high-level language code sequences.
  2. Pritchard, Jeffrey Orion, Allocating hardware resources for high-level language code sequences.
  3. Pritchard, Jeffrey Orion, Allocating hardware resources for high-level language code sequences.
  4. Sandstrom, Mark Henrik, Application load adaptive multi-stage parallel data processing architecture.
  5. Sandstrom, Mark Henrik, Application load adaptive multi-stage parallel data processing architecture.
  6. Sandstrom, Mark Henrik, Application load adaptive multi-stage parallel data processing architecture.
  7. Pessolano, Francesco, Automatic task distribution in scalable processors.
  8. Pritchard,Jeffrey Orion; Wayne,Todd, Generating components on a programmable device using a high-level language.
  9. Pritchard,Jeffrey Orion; Lau,David James; Allen,Timothy P., Hardware acceleration of high-level language code sequences on programmable devices.
  10. Pritchard, Jeffrey Orion; Blackburn, Jarrod Colin James; Lau, David James; Molson, Philippe; Ball, James L.; Kempa, Jesse, High-level language code sequence optimization for implementing programmable chip designs.
  11. Pritchard, Jeffrey Orion; Blackburn, Jarrod Colin James; Lau, David James; Molson, Philippe; Ball, James L.; Kempa, Jesse, High-level language code sequence optimization for implementing programmable chip designs.
  12. Pritchard, Jeffrey Orion; Blackburn, Jarrod Colin James; Lau, David James; Molson, Philippe; Ball, James L.; Kempa, Jesse, High-level language code sequence optimization for implementing programmable chip designs.
  13. Eccles,Robert E., Method and apparatus for design verification with equivalency check.
  14. Janneck, Jorn W.; Parlour, David B.; Schumacher, Paul R., Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit.
  15. Jones, Jakob, Multiple reconfiguration profiles for dynamically reconfigurable intellectual property cores.
  16. Willis, John C., Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set.
  17. Sandstrom, Mark Henrik, Scheduling application instances to configurable processing cores based on application requirements and resource specification.
  18. Pritchard,J. Orion; Wayne,Todd, Scheduling logic on a programmable device implemented using a high-level language.
  19. Sandstrom, Mark Henrik, Scheduling tasks to configurable processing cores based on task requirements and specification.
  20. Jones, Jakob Raymond; Padmanabhan, Prasanna, Selectable reconfiguration for dynamically reconfigurable IP cores.
  21. Jones, Jakob Raymond; Padmanabhan, Prasanna, Selectable reconfiguration for dynamically reconfigurable IP cores.
  22. Baxter,Michael A., System and method for dynamic reconfigurable computing using automated translation.
  23. Huang, Randy R.; Voogel, Martin; Hu, Jingcao; Teig, Steven, System and method for reducing reconfiguration power usage.
  24. Huang, Randy R.; Voogel, Martin; Hu, Jingcao; Teig, Steven, System and method for reducing reconfiguration power usage.
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