IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0672540
(2003-09-26)
|
우선권정보 |
JP-0286637 (2002-09-30) |
발명자
/ 주소 |
- Watanabe, Hiroshi
- Takeda, Kohji
|
인용정보 |
피인용 횟수 :
7 인용 특허 :
5 |
초록
▼
The present invention provides a circuit to shift the level of an arbitrary input signal level higher than the power supply voltage to a reference logic level controlled by the power supply voltage quickly, reliably, and accurately. When a signal input to port A changes from the low level to the hig
The present invention provides a circuit to shift the level of an arbitrary input signal level higher than the power supply voltage to a reference logic level controlled by the power supply voltage quickly, reliably, and accurately. When a signal input to port A changes from the low level to the high level, the potential at node S1 is immediately increased to a potential significantly higher than the power supply voltage due to the capacitive coupling of the drain-gate capacitance of NMOS transistor 10, so that NMOS transistor 14 turns on at bias circuit 12 in order to allow current to flow from node S1 to power supply voltage terminal C, and the potential of node S1 is clamped to level (VCC+VTN14), that is, above power supply voltage VCC by threshold voltage VTN14. As a result, a high level equal to the level below gate potential (VCC+VTN14) by threshold voltage VTN10, that is, the potential of VCC, is obtained at source of NMOS transistor 10, that is, port B.
대표청구항
▼
1. A level shifting circuit comprisinga first MOS transistor whose first terminal is connected to a first port and whose second terminal is connected to a second port, a second MOS transistor of the same conductivity type as the first MOS transistor, whose first terminal is connected to a power supp
1. A level shifting circuit comprisinga first MOS transistor whose first terminal is connected to a first port and whose second terminal is connected to a second port, a second MOS transistor of the same conductivity type as the first MOS transistor, whose first terminal is connected to a power supply voltage terminal that supplies a power supply voltage corresponding to a reference logic level and whose second terminal and gate terminal are both connected to the gate terminal of the first MOS transistor, a bias means for supplying a prescribed bias voltage below the power supply voltage to the gate terminal of the first MOS transistor, a first clamping circuit comprises a first switch which is turned off when the potential levels of the first and second ports have logic levels different from the reference logic level, and it is turned on when the potential of one of the first and the second port has a logic level equal to the reference logic level. 2. The level shifting circuit of claim 1, wherein the first clamping circuit is provided with a first diode for allowing a current to flow in the forward direction from the power supply voltage terminal to the first port.3. The level shifting circuit of claim 2, wherein the first clamping circuit is provided with a first constant current source circuit for allowing a constant current to flow from the power supply voltage terminal to the first port.4. The level shifting circuit of claim 3, comprising a second clamping circuit connected between the power supply voltage terminal and the second port in order to clamp the potential of the second port near the reference logic level.5. The level shifting circuit of claim 4, wherein the second clamping circuit comprises a second switch which is turned off when the potential levels of the first and the second ports have logic levels different from the reference logic level, and it is turned on when the potential of one of the and the second ports is logically equal to the reference logic level.6. The level shifting circuit of claim 5, wherein the second clamping circuit is provided with a second diode for allowing a current to flow in the forward direction from the power supply voltage terminal to the second port.7. The level shifting circuit of claim 4, wherein the second clamping circuit is provided with a second constant current source circuit for allowing a constant current to flow from the power supply voltage terminal to the second port.8. The level shifting circuit of claim 7, comprising a third diode whose anode is connected to the first port, and whose cathode is connected to the gate terminal of the first MOS transistor.9. The level shifting circuit of claim 8, further comprising a first resistor connected in series with the third diode between the first port and the gate terminal of the first MOS transistor.10. The level shifting circuit of claim 8, further comprising a third constant current source circuit connected in series with the third diode between the first port and the gate terminal of the first MOS transistor.11. The level shifting circuit of claim 9, further comprising a fourth diode whose anode is connected to the second port, and whose cathode is connected to the gate terminal of the first MOS transistor.12. The level shifting circuit of claim 11, further comprising a second resistor connected in series with the fourth diode between the second port and the gate terminal of the first MOS transistor.13. The level shifting circuit of claim 11, wherein the bias means is provided with a fifth diode whose anode is connected to the power supply voltage terminal, and whose cathode is connected to the gate terminal of the first MOS transistor.14. The level shifting circuit of claim 13, further comprising a third switch connected in series with the fifth diode the power supply voltage terminal and the gate terminal of the first MOS transistor,a fourth switch connected between the gate terminal of the first MOS transistor and a reference potential logic level different from the reference logic level, and a switch control means that tums the third switch on and the fourth switch off and vice versa. 15. The level shifting circuit of claim 14, further comprising a voltage amplifier which increases the potential of the gate terminal of the first MOS transistor to a level higher than the power supply voltage in response to a control signal given by the switch control means in order to turn the third switch on and turn the fourth switch off.16. The level shifting circuit of claim 15, wherein the voltage amplifier circuit is provided with a delayed voltage output circuit that increases its output voltage from a logic level different from the reference logic level to a logic level equal to the reference logic level after a prescribed delay time has passed after the control signal is input, as well as with a capacitor connected between the output terminal of the delayed voltage output circuit and the gate terminal of the first MOS transistor.17. The level shifting circuit of claim 14, further comprising a third MOS transistor whose first terminal is connected to the first port and whose second terminal is connected to the second port,a fourth MOS transistor of the same conductivity type as the third MOS transistor whose first terminal is connected to the power supply voltage terminal and whose second terminal and gate terminal are both connected to the gate terminal of the third MOS transistor, a sixth diode whose anode is coupled to the power supply voltage terminal and whose cathode is connected to the gate terminal of the third MOS transistor, a fifth switch connected in series with the sixth diode between the power supply voltage terminal and the gate terminal of the third MOS transistor, a sixth switch connected between the gate terminal of the third MOS transistor and a reference potential having a logic level different from the reference logic level, a switch control means that turns the fifth switch on and the sixth switch off and vice versa, and a voltage amplifier that increases the potential of the gate terminal of the third MOS transistor to a level higher than the power supply voltage in response to a control signal given by the switch control means in order to turn the fifth switch on and turn the sixth switch off. 18. The level shifting circuit of the claim 17, wherein the voltage amplifier is provided with a delayed voltage output circuit that increases its output voltage from a logic level different from the reference logic level to a logic level equal to the reference logic level after a prescribed amount of delay time has passed after the control signal is input, as well as with a capacitor connected between the output terminal of the delayed voltage output circuit and the gate terminal of the third MOS transistor.19. A level shifting circuit comprising a first MOS transistor connected between a first input/output terminal and a second input/output terminal,a second MOS transistor connected between a first power supply voltage terminal and the gate terminal of the first MOS transistor and whose gate terminal is connected to the gate terminal of the first MOS transistor, a first rectifying element connected between a first power supply voltage terminal and the gate terminal of the first MOS transistor in order to source current from the first power supply voltage terminal to the gate terminal of the first MOS transistor, a second rectifying element connected between the first input/output terminal and the gate terminal of the first MOS transistor in order to source current from the first input/output terminal to the gate terminal of the first MOS transistor, a third rectifying element connected between the second input/output terminal and the gate terminal of the first MOS transistor in order to source current from the second input/output terminal to the gate terminal of the first MOS transistor, a third MOS transistor connected between the first power supply voltage terminal and the first input/output terminal, a fourth rectifying element connected between the third MOS transistor and the first input/output terminal in order to source current from the first power supply voltage terminal to the first input/output terminal, a fourth MOS transistor connected between the first power supply voltage terminal and the second input/output terminal, a fifth rectifying element connected between the fourth MOS transistor and the second input/output terminal in order to source current from the first power supply voltage terminal to the second input/output terminal, and a logic circuit whose first and second input terminals are connected to the first and the second input/output terminals, respectively, in order to output a control signal to turn on the fourth and fifth MOS transistors when the voltage level of the first and/or the second input/output terminal corresponds to the power supply voltage. 20. The level shifting circuit of claim 19, wherein the first and second MOS transistors are NMOS transistors,the third and fourth MOS transistors are PMOS transistors, the first rectifying element is a diode whose anode is connected to the first power supply voltage terminal and whose cathode is connected to the gate terminal of the first MOS transistor, the second rectifying element is a diode whose anode is connected to the first input/output terminal and whose cathode is connected to the gate terminal of the first MOS transistor, the third rectifying element is a diode whose anode is connected to the second input/output terminal and whose cathode is connected to the gate terminal of the first MOS transistor, the fourth rectifying element is a diode whose anode is connected to the third MOS transistor and whose cathode is connected to the first input/output terminal, and the fifth rectifying element is a diode whose anode is connected to the fourth MOS transistor and whose cathode is connected to the second input/output terminal. 21. The level shifting circuit of claim 19, comprisinga fifth MOS transistor connected between the first rectifying element and the gate terminal of the first MOS transistor in order to cut off the current path formed between the first rectifying element and the gate terminal of the first MOS transistor, the current path between the second rectifying element and the gate terminal of the first MOS transistor, and the current path between the third rectifying element and the gate terminal of the first MOS transistor, a sixth MOS transistor connected between the gate terminal of the first MOS transistor and the second power supply voltage terminal, and a control circuit that supplies a control signal in order to make the fifth MOS transistor and the sixth MOS transistor conductive in a complementary manner.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.