초록 ▼

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of ma

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

대표청구항 ▼

1. For an array of electrically alterable memory cells divided into blocks of cells that are re-settable together to a starting state and having means for addressing individual cells within said blocks to program and read their states, said memory cells individually including a field effect transist

1. For an array of electrically alterable memory cells divided into blocks of cells that are re-settable together to a starting state and having means for addressing individual cells within said blocks to program and read their states, said memory cells individually including a field effect transistor having a threshold voltage level that is variable in accordance with an amount of net charge stored therein, a method of operating the array, comprising the steps of:establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of detectable states of the individual cells in excess of two, programming the effective threshold voltage level of at least one addressed cell within one of said blocks from a starting level to one of the plurality of effective threshold voltage levels by altering the amount of charge stored in said at least one addressed cell until the effective threshold voltage of said at least one addressed cell is substantially equal to one of said plurality of effective threshold voltage levels, wherein the state of said at least one addressed cell is set to one of said plurality of states by a method comprising: applying a given voltage to said addressed cell for a predetermined time sufficient to move the effective threshold voltage level of the addressed cell from the starting level toward said one of the plurality of threshold voltage levels, thereafter reading an electrical parameter of the addressed cell to determine whether the effective threshold voltage of the addressed cell has reached said of the plurality of threshold voltage levels, and repeating the voltage applying and reading steps until it is detected by reading step that the effective threshold voltage of the addressed cell has been set to said one of the plurality of threshold voltage levels, reading the states of the memory cells of individual blocks with the assistance of an error correction scheme that can tolerate a number X of bad cells, and applying erase conditions to the memory cells of individual blocks until a number of cells N remaining unerased is equal to or less than X. 2. The method according to claim 1, wherein the step of establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels.3. The method according to claim 1, wherein at least two of the plurality of effective threshold voltage levels in excess of two result from a net positive charge the individual cells.