$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method of fabricating flexible circuits for integrated circuit interconnections 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01K-003/10
출원번호 US-0514762 (2000-02-28)
발명자 / 주소
  • Abbott, Donald C.
  • Cotugno, John E.
  • Fritzsche, Robert M.
  • Sabo, Robert A.
  • Sullivan, Christopher M.
  • West, David W.
출원인 / 주소
  • Texas Instruments Incorporated
인용정보 피인용 횟수 : 16  인용 특허 : 17

초록

A method for the fabrication of a double-sided electrical interconnection flexible circuit (200) particularly useful as a substrate for an area array integrated circuit package. A copper matrix with studs (203) is pressed through a dielectric film (201) having a copper layer on the opposite surface,

대표청구항

1. A method of manufacturing a flex circuit on a flexible base polymer film including the steps of:a) superimposing on said film an embossing tool having raised areas comprising a pattern of conductors and vias corresponding to a circuit design, wherein, said raised areas are coated with a thin laye

이 특허에 인용된 특허 (17)

  1. Tokuda Masahide,JPX ; Kato Takeshi,JPX ; Itoh Hiroyuki,JPX ; Yagyu Masayoshi,JPX ; Fujita Yuuji,JPX ; Usami Mitsuo,JPX, Chip connection structure having diret through-hole connections through adhesive film and wiring substrate.
  2. Inoue Tatsuo,JPX, Chip size package.
  3. Odaira Hiroshi (Chigasaki JPX) Imamura Eiji (Yokosuka JPX) Wada Yusuke (Tokyo JPX) Arai Yasushi (Fujisawa JPX) Sasaoka Kenji (Zama JPX) Mori Takahiro (Yokohama JPX) Ikegaya Fumitoshi (Zama JPX) Kowat, Circuit devices and fabrication method of the same.
  4. Zimmerman Richard Henry (Palmyra PA), Conductor patterned substrate providing stress release during direct attachment of integrated circuit chips.
  5. Kasubuchi Takeshi (Nara JPX) Ozawa Kaoru (Yamatokoriyama JPX) Hara Takeo (Ikoma JPX), Electronic control assembly mounted on a flexible carrier and manufacture thereof.
  6. Sumi Shinji,JPX ; Wakashima Kouichi,JPX, Fabrication method of multilayer printed wiring board.
  7. Miles Barry M. (Plantation FL) Juskey Frank J. (Coral Springs FL) Banerji Kingshuk (Plantation FL), Leadless integrated circuit package.
  8. Lau John H., Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips.
  9. Hayakawa, Masao; Maeda, Takamichi; Oda, Mituwo, Method of making a through-hole connector.
  10. Chong Ku Ho ; Crockett ; Jr. Charles Hayden ; Dunn ; deceased Stephen Alan ; Hoebener Karl Grant ; McMaster Michael George, Method of manufacturing a multiple layer circuit board die carrier with fine dimension stacked vias.
  11. Motomura Tomohisa,JPX ; Shimada Osamu,JPX ; Fukuoka Yoshitaka,JPX, Method of producing a high-density printed wiring board for mounting.
  12. Sasaoka Kenji,JPX ; Odaira Hiroshi,JPX ; Fujiwara Madoka,JPX ; Ikegaya Fumitoshi,JPX ; Mori Takahiro,JPX, Multilayer wiring board and method for forming the same.
  13. Feilchenfeld Natalie Barbara ; Kresge John Steven ; Moore Scott Preston ; Nowak Ronald Peter ; Wilson James Warren, Polytetrafluoroethylene thin film chip carrier.
  14. Ishikawa Kazumitsu (Hiratsuka JPX) Suzuki Haruo (Odawara JPX) Oikawa Shoji (Odawara JPX), Printed wiring board and process for producing the same.
  15. Yamamoto Yuichi,JPX ; Sato Yoshizumi,JPX ; Motomura Tomohisa,JPX ; Hamano Hiroshi,JPX ; Arai Yasushi,JPX, Printed wiring board having an interconnection penetrating an insulating layer.
  16. Palmer David W. ; Gassman Richard A. ; Chu Dahwey, Silicon ball grid array chip carrier.
  17. Tajima Naoyuki (Nara JPX) Tsuda Takaaki (Tenri JPX) Chikawa Yasunori (Nara JPX), Tape carrier for semiconductor chips.

이 특허를 인용한 특허 (16)

  1. Richardson, Brian Edward, Deionizing fluid filter devices and methods of use.
  2. Chen, Shou Lung; Hsiao, Ching Wen; Chen, Yu Hua; Ko, Jeng Dar; Lin, Jyh Rong, Electronic device package and method of manufacturing the same.
  3. Chen, Shou-Lung; Hsiao, Ching-Wen; Chen, Yu-Hua; Ko, Jeng-Dar; Lin, Jyh-Rong, Electronic device package and method of manufacturing the same.
  4. Richardson, Brian E., Fluid filters and methods of use.
  5. Smith, Timothy J.; Wang, Tzu-Yu; Eskridge, Adam Z., Insert molded actuator components.
  6. Chen,Huei Jen; Liu,Evan; Chen,Yvon, Method for fabricating a substrate, including a plurality of chip package substrates.
  7. Nakamura, Junichi; Kobayashi, Yuji, Method of fabricating wiring board and method of fabricating semiconductor device.
  8. Richardson, Brian Edward, Microstructure separation filters.
  9. Wang, Chien-Hao, Process for manufacturing substrate with bumps and substrate structure.
  10. Abbott,Donald C., Semiconductor assembly having substrate with electroplated contact pads.
  11. Abbott,Donald C., Semiconductor assembly having substrate with electroplated contact pads.
  12. Kawano, Masaya; Soejima, Koji; Kurita, Yoichiro, Semiconductor device and method of manufacturing the same.
  13. Kawano, Masaya; Soejima, Koji; Kurita, Yoichiro, Semiconductor device and method of manufacturing the same.
  14. Kim, Chunho; Shi, Songhua; Ricotta, Mark S.; Sleeper, Scott B.; Wang, Yongqian, Systems for encapsulating a hybrid assembly of electronic components and associated methods.
  15. Richardson, Brian Edward, Three dimensional nanometer filters and methods of use.
  16. Nakamura, Junichi; Kobayashi, Yuji, Wiring board and semiconductor device.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로