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Method for bonding IC chips to substrates incorporating dummy bumps and non-conductive adhesive and structures formed 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0190276 (2002-07-05)
발명자 / 주소
  • Hsieh, Yu-Te
  • Chang, Shyh-Ming
  • Lin, Wen-Ti
출원인 / 주소
  • Industrial Technology Research Institute
대리인 / 주소
    Akin Gump Strauss Hauer &
인용정보 피인용 횟수 : 46  인용 특허 : 4

초록

An IC chip/substrate assembly bonded together by a non-conductive adhesive and a method for forming the assembly. The assembly consists of an IC chip that has bumps formed on an active surface, a substrate that has bond pads formed on a top surface, wherein at least one of the IC chip and the substr

대표청구항

1. An IC chip/substrate assembly comprising:an IC chip having connection bumps and at least one dummy bump formed over an active surface; a substrate having bond pads and at least one dummy bump formed over a top surface; and a non-conductive adhesive disposed in-between said IC chip and said substr

이 특허에 인용된 특허 (4)

  1. Williams Ronald L. (San Marcos CA) Tyra Joe B. (Carlsbad CA), Apparatus and method for protecting metal bumped integrated circuit chips during processing and for providing mechanical.
  2. Hikita, Junichi; Nakatani, Goro; Kumamoto, Nobuhisa; Sameshima, Katsumi; Shibata, Kazutaka; Ueda, Shigeyuki, Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device.
  3. Junichi Hikita JP; Hiroo Mochida JP; Goro Nakatani JP; Kazutaka Shibata JP, Semiconductor chip and semiconductor device having a chip-on-chip structure.
  4. Kawakita Tetsuo,JPX ; Matsumura Kazuhiko,JPX ; Yamane Ichiro,JPX, Semiconductor device having improved test electrodes.

이 특허를 인용한 특허 (46)

  1. Trezza, John, Back-to-front via process.
  2. Lu,Su Tsai, Bonding structure of device packaging.
  3. Kobayashi,Kazuo; Yajima,Hidehiko, Bumped IC, display device and electronic device using the same.
  4. Trezza, John, Chip capacitive coupling.
  5. Trezza, John, Chip capacitive coupling.
  6. Trezza, John; Callahan, John; Dudoff, Gregory, Chip connector.
  7. Trezza, John, Chip spanning connection.
  8. Trezza, John, Chip-based thermo-stack.
  9. Trezza, John, Chip-based thermo-stack.
  10. Trezza, John, Coaxial through chip connection.
  11. Trezza, John; Callahan, John; Dudoff, Gregory, Contact-based encapsulation.
  12. Shih, Ying-Ching; Lu, Szu Wei; Lin, Jing-Cheng, Dam structure for enhancing joint yield in bonding processes.
  13. Wu, Chih-Wei; Lu, Szu Wei; Lin, Jing-Cheng, Die-on-interposer assembly with dam structure and method of manufacturing the same.
  14. Trezza, John, Electrically conductive interconnect system and method.
  15. Trezza, John; Callahan, John; Dudoff, Gregory, Electronic chip contact structure.
  16. Trezza, John, Front-end processed wafer having through-chip connections.
  17. Trezza, John, Inverse chip connector.
  18. Trezza, John, Inverse chip connector.
  19. Trezza, John, Isolating chip-to-chip contact.
  20. Trezza, John, Isolating chip-to-chip contact.
  21. Dotsenko, Vladimir V., Method for fabrication of electrical contacts to superconducting circuits.
  22. Myers,Bruce A.; Ihms,David W.; Oman,Todd P., Method of fabricating an electronic package having underfill standoff.
  23. Kim, Oh Han; Kim, BaeYong; Kim, YoungMin, Mock bump system for flip chip integrated circuits.
  24. Kim, YoungMin; Kim, BaeYong; Kang, HyunChul, Mock bump system for flip chip integrated circuits.
  25. Lebonheur, Vassoudevane; Harries, Richard J., Mold compound cap in a flip chip multi-matrix array package and process of making same.
  26. Lebonheur,Vassou; Harries,Richard J., Mold compound cap in a flip chip multi-matrix array package and process of making same.
  27. Trezza, John; Callahan, John; Dudoff, Gregory, Patterned contact.
  28. Trezza, John; Frushour, Ross, Pin-type chip tooling.
  29. Trezza, John, Plated pillar package formation.
  30. Trezza, John; Callahan, John; Dudoff, Gregory, Post & penetration interconnection.
  31. Trezza, John, Process for chip capacitive coupling.
  32. Trezza, John, Processed wafer via.
  33. Trezza, John, Processed wafer via.
  34. Trezza, John; Callahan, John; Dudoff, Gregory, Profiled contact.
  35. Trezza, John, Remote chip attachment.
  36. Trezza, John, Remote chip attachment.
  37. Trezza, John; Frushour, Ross, Rigid-backed, membrane-based chip tooling.
  38. Misra, Abhay; Trezza, John, Routingless chip architecture.
  39. Chen, Yu-Feng; Wu, Kai-Chiang; Lu, Chun-Lin; Kou, Hung-Jui, Semiconductor devices and methods of manufacture thereof.
  40. Trezza, John, Side stacking apparatus and method.
  41. Daubenspeck, Timothy Harrison; Gambino, Jeffrey Peter; Muzzy, Christopher David; Sauter, Wolfgang, Substrate anchor structure and method.
  42. Dotsenko, Vladimir V., Superconductive multi-chip module for high speed digital circuits.
  43. Trezza, John, Thermally balanced via.
  44. Dugas, Roger; Trezza, John, Tooling for coupling multiple electronic chips.
  45. Trezza, John, Triaxial through-chip connection.
  46. Trezza, John, Triaxial through-chip connection.
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