Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/336
H01L-021/469
출원번호
US-0209581
(2002-07-30)
발명자
/ 주소
Ahn, Kie Y.
Forbes, Leonard
출원인 / 주소
Micron Technology Inc.
대리인 / 주소
Schwegman, Lundberg, Woessner &
인용정보
피인용 횟수 :
203인용 특허 :
66
초록▼
A dielectric film containing HfO2/ZrO2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer deposition of HfO2 using a HfI4 precursor fo
A dielectric film containing HfO2/ZrO2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer deposition of HfO2 using a HfI4 precursor followed by the formation of ZrO2 on the HfO2 layer. The HfO2 layer thickness is controlled by repeating for a number of cycles a sequence including pulsing the HfI4 precursor into a reaction chamber, pulsing a purging gas into the reaction chamber, pulsing a first oxygen containing precursor into the reaction chamber, and pulsing the purging gas until the desired thickness is formed. These gate dielectrics containing HfO2/ZrO2 nanolaminates are thermodynamically stable such that the HfO2/ZrO2 nanolaminates will have minimal reactions with a silicon substrate or other structures during processing.
대표청구항▼
1. A method of forming a dielectric film comprising:forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor; and forming a layer of zirconium oxide on the layer of hafnium oxide to form a HfO2/ZrO2 composite, wherein the HfO2/ZrO2 compo
1. A method of forming a dielectric film comprising:forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor; and forming a layer of zirconium oxide on the layer of hafnium oxide to form a HfO2/ZrO2 composite, wherein the HfO2/ZrO2 composite is a nanolaminate having a final layer of hafnium oxide and an initial layer of hafnium oxide on the substrate. 2. The method of claim 1, wherein forming a layer of hafnium oxide on a substrate by atomic layer deposition using a HfI4 precursor includes pulsing a first oxygen containing precursor into the reaction chamber after pulsing the HfI4 precursor into the reaction chamber.3. The method of claim 2, wherein the first oxygen precursor is water vapor.4. The method of claim 2, the method further including pulsing nitrogen gas into the reaction chamber as a purging gas between pulsing the HfI4 precursor into the reaction chamber and pulsing the first oxygen containing precursor into the reaction chamber, and after pulsing the first oxygen containing precursor into the reaction chamber.5. The method of claim 1, wherein forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor includes performing a predetermined number of cycles of atomic layer deposition of hafnium oxide.6. A method of forming a dielectric film comprising:forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor; and forming a layer of zirconium oxide on the layer of hafnium oxide by atomic layer deposition to form a HfO2/ZrO2 composite, wherein the HfO2/ZrO2 composite is a nanolaminate having a final layer of hafnium oxide and an initial layer of hafnium oxide on the substrate. 7. The method of claim 6, wherein forming a layer of zirconium oxide on the layer of hafnium oxide by atomic layer deposition includes using a ZrI4 precursor.8. The method of claim 6, wherein forming a layer of zirconium oxide on the layer of hafnium oxide by atomic layer deposition includes pulsing an oxygen containing precursor into the reaction chamber after pulsing a zirconium precursor into the reaction chamber.9. The method of claim 8, wherein pulsing an oxygen containing precursor includes pulsing a vapor solution of H2O?H2O2.10. The method of claim 8, the method further including pulsing nitrogen gas into the reaction chamber as a purging gas between pulsing precursors into the reaction chamber.11. The method of claim 8, wherein pulsing each precursor into the reaction chamber is controlled for a predetermined period, the predetermined period being individually controlled for each precursor pulsed into the reaction chamber.12. The method of claim 6, wherein the method further includes maintaining the substrate at a selected temperature for forming each layer, the selected temperature set independently for forming each layer.13. The method of claim 6, wherein forming a layer of zirconium oxide on the layer of hafnium oxide includes forming a completed HfO2/ZrO2 dielectric film having a thickness where the HfO2 layer has a thickness that is about one-half the thickness of the completed HfO2/ZrO2 dielectric film.14. A method of forming a transistor comprising:forming first and second source/drain regions in a substrate; forming a body region between the first and second source/drain regions; forming a dielectric film on the body region between the first and second source/drain regions; and coupling a gate to the dielectric film, wherein forming the dielectric film on the body region includes: forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor; and forming a layer of zirconium oxide on the layer of hafnium oxide to form a HfO2/ZrO2 composite, wherein the HfO2/ZrO2 composite is a nanolaminate having a final layer of hafnium oxide and an initial layer of hafnium oxide on the substrate. 15. The method of claim 14, wherein forming a layer of zirconium oxide includes forming a layer of zirconium oxide by atomic layer deposition.16. A method of forming a memory array comprising:forming a number of access transistors, at least one of the access transistors including a dielectric film containing a HfO2/ZrO2 nanolaminate on a body region between a first and second source/drain regions, the HfO2/ZrO2 nanolaminate having a final layer of hafnium oxide and an initial layer of hafnium oxide on the body region, the dielectric film containing a HfO2/ZrO2 nanolaminate formed by a method including: forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor; and forming a layer of zirconium oxide on the layer of hafnium oxide; forming a number of word lines coupled to a number of the gates of the number of access transistors; forming a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; and forming a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors. 17. The method of claim 16, wherein forming a layer of zirconium oxide includes forming a layer of zirconium oxide by atomic layer deposition.18. A method of forming an electronic system comprising:providing a processor; coupling a memory array to the processor, wherein the memory array includes at least one access transistor having a dielectric film containing a HfO2/ZrO2 nanolaminate on a body region between a first and second source/drain regions, the HfO2/ZrO2 nanolaminate having a final layer of hafnium oxide and an initial layer of hafnium oxide on the body region, the dielectric film containing a HfO2/ZrO2 nanolaminate formed by a method including: forming a layer of hafnium oxide on a substrate in a reaction chamber by atomic layer deposition using a HfI4 precursor; and forming a layer of zirconium oxide on the layer of hafnium oxide; and forming a system bus that couples the processor to the memory array. 19. The method of claim 18, wherein forming a layer of zirconium oxide includes forming a layer of zirconium oxide by atomic layer deposition.20. The method of claim 15, wherein forming a layer of zirconium oxide by atomic layer deposition includes forming the layer of zirconium oxide using a zirconium halide precursor.21. The method of claim 17, wherein forming a layer of zirconium oxide by atomic layer deposition includes forming the layer of zirconium oxide using a zirconium halide precursor.22. The method of claim 19, wherein forming a layer of zirconium oxide by atomic layer deposition includes forming the layer of zirconium oxide using a zirconium halide precursor.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (66)
Kopacz Stanislaw ; Webb Douglas Arthur ; Leusink Gerrit Jan ; LeBlanc Rene Emile ; Ameen Michael S. ; Hillman Joseph Todd ; Foster Robert F. ; Rowan ; Jr. Robert Clark, Apparatus and method for preventing the premature mixture of reactant gases in CVD and PECVD reactions.
Visokay, Mark Robert; Rotondaro, Antonio Luis Pacheco; Colombo, Luigi, Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing.
Moise Theodore S. ; Xing Guoqiang ; Visokay Mark ; Gaynor Justin F. ; Gilbert Stephen R. ; Celii Francis ; Summerfelt Scott R. ; Colombo Luigi, Integrated circuit and method.
Glassman Timothy E. (Danbury CT) Chayka Paul V. (New Milford CT), Lanthanide/phosphorus precursor compositions for MOCVD of lanthanide/phosphorus oxide films.
Kirlin Peter S. ; Brown Duncan W. ; Baum Thomas H. ; Vaarstra Brian A. ; Gardiner Robin A., Metal complex source reagents for chemical vapor deposition.
Bauer Mark E. ; Wells Steven ; Brown David M. ; Javanifard Johnny ; Sweha Sherif ; Hasbun Robert N. ; Gallagher Gary J. ; Rashid Mamun ; Rozman Rodney R. ; Hawk Glen ; Blanchard George ; Winston Mark, Method and circuitry for usage of partially functional nonvolatile memory.
Jong-myeong Lee KR; Hyun-seok Lim KR; Byung-hee Kim KR; Gil-heyun Choi KR; Sang-in Lee KR, Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby.
Bhattacharyya Arup (Essex Junction VT) Chu Wei-Kan (Poughkeepsie NY) Howard James K. (Fishkill NY) Wiedman Francis W. (Stowe VT), Method for manufacture of ultra-thin film capacitor.
Gardiner Robin A. ; Kirlin Peter S. ; Baum Thomas H. ; Gordon Douglas ; Glassman Timothy E. ; Pombrik Sofia ; Vaartstra Brian A., Method of forming metal films on a substrate by chemical vapor deposition.
Pekka J. Soininen FI; Kai-Erik Elers FI; Suvi Haukka FI, Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH.
Arvind Halliyal ; Robert Bertram Ogle, Jr. ; Joong S. Jeon ; Fred Cheung ; Effiong Ibok, Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material.
Umotoy Salvador P. ; Lei Lawrence C. ; Nguyen Anh N. ; Chiao Steve H., One-piece dual gas faceplate for a showerhead in a semiconductor wafer processing system.
Senzaki, Yoshihide; Hochberg, Arthur Kenneth; Norman, John Anthony Thomas, Process for metal metalloid oxides and nitrides with compositional gradients.
Shiraiwa, Hidehiko; Park, Jaeyong; Cheung, Fred T K; Halliyal, Arvind, Process for reducing hydrogen contamination in dielectric materials in memory devices.
Gardner Mark I. ; Fulford H. Jim ; May Charles E. ; Hause Fred ; Kwong Dim-Lee, Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof.
Fujikawa Yuichiro (Yamanashi-ken JPX) Hatano Tatsuo (Yamanashi-ken JPX) Murakami Seishi (Yamanashi-ken JPX), Shower head and film forming apparatus using the same.
Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
Brask, Justin K.; Doyle, Brian S.; Kavalieros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material.
Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
Park, Ki Yeon; Yoon, Kyoung Ryul; Choi, Dae Sik; Choi, Han Mei; Lee, Seung Hwan, Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same.
Park, Ki-Yeon; Yoon, Kyoung-Ryul; Choi, Dae-Sik; Choi, Han-Mei; Lee, Seung-Hwan, Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same.
Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.