초록 ▼

This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements.

This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

대표청구항 ▼

1. A method of forming an integrated circuit device, comprising:forming an access transistor, a gate electrode of said access transistor comprising a midgap material comprising at least two material components; forming at least one NMOS periphery transistor, said at least one NMOS periphery transist

1. A method of forming an integrated circuit device, comprising:forming an access transistor, a gate electrode of said access transistor comprising a midgap material comprising at least two material components; forming at least one NMOS periphery transistor, said at least one NMOS periphery transistor comprising a gate electrode layer comprising a midgap material having at least two material components; and forming at least one PMOS periphery transistor, said at least one PMOS periphery transistor comprising a gate electrode layer comprising a midgap material having at least two material components, wherein the workfunction of each said gate electrode is set at least in part by the mole fraction of said midgap material components in said gate electrodes, and wherein the step of forming an access transistor further comprises the step of depositing a layer of polysilicon over said midgap material. 2. The method of claim 1, further comprising the step of forming a dielectric layer over said polysilicon layer.3. The method of claim 1, wherein the step of forming an access transistor further comprises the step of forming a layer comprising silicide over said midgap material.4. A method of forming an integrated circuit device, comprising:forming an access transistor, a gate electrode of said access transistor comprising a midgap material comprising at least two material components; forming at least one NMOS periphery transistor, said at least one NMOS periphery transistor comprising a gate electrode layer comprising a midgap material having at least two material components; and forming at least one PMOS periphery transistor, said at least one PMOS periphery transistor comprising a gate electrode layer comprising a midgap material having at least two material components, wherein the workfunction of each said gate electrode is set at least in part by the mole fraction of said midgap material components in said gate electrodes, and wherein the step of forming said gate electrode layer of at least one of said periphery transistors comprises depositing a layer of midgap material comprising silicon germanium. 5. The method of claim 4, wherein said deposited layer of midgap material has a mole fraction in the range of about 0.2 to about 0.7 Ge.6. A method of forming an integrated circuit device, comprising:forming an access transistor, a gate electrode of said access transistor comprising a midgap material comprising at least two material components; forming at least one NMOS periphery transistor, said at least one NMOS periphery transistor comprising a gate electrode layer comprising a midgap material having at least two material components; forming at least one PMOS periphery transistor, said at least one PMOS periphery transistor comprising a gate electrode layer comprising a midgap material having at least two material components, wherein the workfunction of each said gate electrode is set at least in part by the mole fraction of said midgap material components in said gate electrodes; and doping a channel region in said substrate corresponding to each of said access, NMOS and PMOS transistors. 7. The method of claim 6, further comprising the step of doping each said channel region, wherein the amount of doping depends on the mole fraction of the material components of said midgap material in said gate electrode layer.8. The method of claim 6, wherein two of said at least two material components are silicon and germanium.9. A method of forming an integrated circuit device, comprising:forming an access transistor, a gate electrode of said access transistor comprising a midgap material comprising at least two material components; forming at least one NMOS periphery transistor, said at least one NMOS periphery transistor comprising a gate electrode layer comprising a midgap material having at least two material components; and forming at least one PMOS periphery transistor, said at least one PMOS periphery transistor comprising a gate electrode layer comprising a midgap material having at least two material components, wherein the workfunction of each said gate electrode is set at least in part by the mole fraction of said midgap material components in said gate electrodes, and wherein said gate electrode layer of said at least one NMOS transistor and said PMOS transistor further comprises polysilicon. 10. A method of forming an access transistor for an integrated circuit device, said method comprising:forming an oxide layer over a semiconductor substrate; forming a gate electrode layer comprising a midgap material containing at least two material components over said oxide layer, wherein a threshold voltage of said gate electrode of said access transistor is set at least in part by the mole fraction of said midgap material components, said forming a gate electrode comprising forming a layer of silicon germanium by chemical vapor deposition; forming a conductive cap layer over the gate electrode layer; and forming a dielectric layer over said conductive cap layer. 11. The method of claim 8, wherein the step of forming a layer of silicon germanium comprises the acts of:depositing a layer of polysilicon; and implanting germanium into the polysilicon layer. 12. The method of claim 10, wherein the layer of silicon germanium has a mole fraction within the range of about 0.2 to about 0.7 Ge.13. The method of claim 1, wherein two of said at least two material components are silicon and germanium.