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Method for making interconnects and diffusion barriers in integrated circuits

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0093898 (2002-03-08)
발명자 / 주소
  • Dubin, Valery
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Schwegman, Lundberg, Woessner &
인용정보 피인용 횟수 : 11  인용 특허 : 34

초록

The inventor devised methods of forming interconnects that result in conductive structures with fewer voids and thus reduced electrical resistance. One embodiment of the method starts with an insulative layer having holes and trenches, fills the holes using a selective electroless deposition, and fi

대표청구항

1. A method of forming one or more conductive structures for an integrated circuit, the method comprising:providing a solution including at least one surfactant and at least one metal, with the solution having a surfactant concentration; and forming an insulative structure having at least one hole a

이 특허에 인용된 특허 (34)

  1. Bruni Marie-Dominique,FRX, Anode for a flat display screen.
  2. Peijun Ding ; Tony Chiang ; Imran Hashim ; Bingxi Sun ; Barry Chin, Copper alloy seed layer for copper metallization.
  3. Douglas Monte A. (Coppell TX), Copper dry etch process using organic and amine radicals.
  4. Edelstein Daniel Charles ; Harper James McKell Edwin ; Hu Chao-Kun ; Simon Andrew H. ; Uzoh Cyprian Emeka, Copper interconnection structure incorporating a metal seed layer.
  5. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  6. Feldman Leonard C. (Berkeley Heights NJ) Higashi Gregg S. (Basking Ridge NJ) Mak Cecilia Y. (Bedminster NJ) Miller Barry (Murray Hill NJ), Fabrication of electronic devices by electroless plating of copper onto a metal silicide.
  7. Nakano Tadashi (Chiba JPX) Ono Hideaki (Chiba JPX), Interconnection structure for semiconductor integrated circuit and manufacture of the same.
  8. Kapoor Ashok K. (Palo Alto CA) Pasch Nicholas F. (Pacifica CA), Low dielectric constant insulation layer for integrated circuit structure and method of making same.
  9. Schmitt Jerome J. (265 College St. (12N) New Haven CT 06510), Method and apparatus for the deposition of solid films of a material from a jet stream entraining the gaseous phase of s.
  10. Svendsen Leo Gulvad (Redwood City CA) Walker Clifford James (Fremont CA) Lykins ; II James Leborn (San Jose CA), Method for electroplating a substrate containing an electroplateable pattern.
  11. Dubin Valery ; Ting Chiu, Method for fabricating copper-aluminum metallization.
  12. Fitzsimmons John A. (Poughkeepsie NY) Havas Janos (Hopewell Junction NY) Lawson Margaret J. (Newburgh NY) Leonard Edward J. (Fishkill NY) Rhoads Bryan N. (Pine Bush NY), Method for forming patterned films on a substrate.
  13. Andricacos Panayotis Constantinou ; Deligianni Hariklia ; Harper James McKell Edwin ; Hu Chao-Kun ; Pearson Dale Jonathan ; Reynolds Scott Kevin ; Tu King-Ning ; Uzoh Cyprian Emeka, Method of making copper alloys for chip and package interconnections.
  14. Canaperi Donald F. (Bridgewater CT) Jagannathan Rangarajan (Patterson NY) Krishnan Mahadevaiyer (Hopewell Junction NY), Method of replenishing electroless gold plating baths.
  15. Baron William J. (Franklin Township ; Somerset County NJ) Kenney John T. (Lawrence Township ; Mercer County NJ) Townsend Wesley P. (Princeton Township ; Mercer County NJ), Method of selectively depositing a metal on a surface.
  16. Carey David H. (Austin TX), Methods of forming channels and vias in insulating layers.
  17. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  18. Schmitt ; III Jerome J. (New Haven CT) Halpern Bret L. (Bethany CT), Microwave plasma assisted supersonic gas jet deposition of thin film materials.
  19. Misawa Nobuhiro (Kawasaki JPX), Process for fabricating integrated circuit devices.
  20. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
  21. Nair Krishna K. (Binghamton NY) Snyder Keith A. (Vestal NY), Process for making multilayer integrated circuit substrate.
  22. Tokunaga Takafumi (Tokorozawa JPX) Tsuneoka Masatoshi (Ohme JPX) Mizukami Koichiro (Akishima JPX), Process for producing semiconductor integrated circuit device having copper interconnections and/or wirings, and device.
  23. Cheung Robin W. (Cupertino CA) Chang Mark S. (Los Altos CA), Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and h.
  24. Tsu Robert (Dallas TX), Reliability enhancement of aluminum interconnects by reacting aluminum leads with a strengthening gas.
  25. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  26. Matsumoto Yoshishige,JPX ; Ohnishi Yoshitake,JPX ; Endo Kazuhiko,JPX ; Tatsumi Toru,JPX, Semiconductor device and manufacturing method of the same.
  27. Ishigaki Yoshiyuki (Hyogo JPX), Semiconductor device and method for manufacturing the same.
  28. Yamada Masaki,JPX ; Anand Minakshisundaran Balasubramanian,JPX ; Shibata Hideki,JPX, Semiconductor device and method for manufacturing the same.
  29. Arita Koji,JPX ; Fujii Eiji,JPX ; Shimada Yasuhiro,JPX ; Uemoto Yasuhiro,JPX ; Nasu Toru,JPX ; Matsuda Akihiro,JPX ; Nagano Yoshihisa,JPX ; Inoue Atsuo,JPX ; Matsuura Taketoshi,JPX ; Otsuki Tatsuo,JP, Semiconductor device having capacitor and manufacturing method thereof.
  30. Hosomi Eiichi,JPX ; Tazawa Hiroshi,JPX ; Takubo Chiaki,JPX ; Shibasaki Koji,JPX, Semiconductor device, method of fabricating the same and copper leads.
  31. Shinkawata Hiroki,JPX, Semiconductor memory including stacked capacitor having a flat surface.
  32. Shirk Albert (Palmyra PA) Ceresa Myron (Advance NC), Sensitized polyimides and circuit elements thereof.
  33. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  34. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (11)

  1. Anderson, Felix; He, Zhong-Xiang; Stamper, Anthony K., Composite copper wire interconnect structures and methods of forming.
  2. Li, Baozhen; Yang, Chih-Chao, Dual damascene structure with liner.
  3. Li, Baozhen; Yang, Chih-Chao, Dual damascene structure with liner.
  4. Kim, Heong Jin; Kim, Sung Jin, Dual metal interconnection.
  5. Yang, Chih-Chao; Horak, David V.; Koburger, III, Charles W.; Ponoth, Shom, Hybrid copper interconnect structure and method of fabricating same.
  6. Yang, Chih-Chao; Horak, David V.; Koburger, III, Charles W.; Ponoth, Shom, Hybrid copper interconnect structure and method of fabricating same.
  7. Kolics, Artur, Methods and materials for anchoring gapfill metals.
  8. Kolics, Artur, Methods and materials for anchoring gapfill metals.
  9. Morgan, Paul A.; Sinha, Nishant, Selective metal deposition over dielectric layers.
  10. Morgan, Paul A; Sinha, Nishant, Selective metal deposition over dielectric layers.
  11. Morgan, Paul A; Sinha, Nishant, Selective metal deposition over dielectric layers.
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