[특허]Integrated circuit having integrated programmable gate array and method of operating the same

Integrated circuit having integrated programmable gate array and method of operating the same 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-019/00
출원번호	US-0106432 (2002-03-26)
발명자 / 주소	Bemanian, Majid Scharf, William D.
출원인 / 주소	LSI Logic Corporation
대리인 / 주소	Hitt Gaines, P.C.
인용정보	피인용 횟수 : 0 인용 특허 : 17

초록 ▼

An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a programmable gate array (PGA) coupled to the at least two interfaces for communicating data therebetween and, optionally (3) a field-programmable gate array (FPGA) coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment.

대표청구항 ▼

1. An integrated circuit (IC), comprising:at least two interfaces;a programmable gate array (PGA) configured with at least a portion of a design during fabrication of said IC and coupled to said at least two interfaces for communicating data therebetween; andan optional field-programmable gate array (FPGA) having a configuration memory associated therewith and coupled to and configured to cooperate with said PGA to adapt said IC to a particular surrounding environment.2. The IC as recited in claim 1 further comprising a standard input-output interface.3. The IC as recited in claim 1 further comprising a second standard input-output interface.4. The IC as recited in claim 1 further comprising a double data rate interface.5. The IC as recited in claim 1 further comprising a co-processor coupled to embedded memory.6. The IC as recited in claim 1 wherein said at least two interfaces are selected from the group consisting of:a system physical interface (SPI), anda 10-Gigabit Attachment Unit Interface (XAUI).7. The IC as recited in claim 1 further comprising a bus expander coupled to said PGA.8. A method of manufacturing an integrated circuit (IC) suited for a particular application, comprising:forming an integrated circuit having a substrate, at least two interfaces, an optional field-programmable gate array (FPGA) and a programmable gate array (PGA);configuring said PGA during said manufacturing with at least a portion of a design; andsubsequently providing a configuration program to configure said FPGA to cooperate with said PGA to adapt said IC to a particular surrounding environment.9. The method as recited in claim 8 further comprising forming a standard input-output interface on said substrate.10. The method as recited in claim 8 further comprising forming a second standard input-output interface on said substrate.11. The method as recited in claim 8 further comprising forming a double data rate interface on said substrate.12. The method as recited in claim 8 further comprising forming a co-processor on said substrate.13. The method as recited in claim 8 wherein said at least two interfaces are selected from the group consisting of:a system physical interface (SPI), anda 10-Gigabit Attachment Unit Interface (XAUI).14. The method as recited in claim 8 further comprising forming a bus expander on said substrate.

이 특허에 인용된 특허 (17)

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Leitch, James R., Data processing system with improved latency and associated methods.
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Dobbelaere Ivo J. (Palo Alto CA) El Gamal Abbas (Palo Alto CA), Electrically programmable inter-chip interconnect architecture.
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Taguchi, Hideki, Electronic circuit device and hybrid integrated circuit with an ASIC and an FPGA.
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Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
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Schultz David P. ; Hung Lawrence C. ; Goetting F. Erich, Method and structure for configuring FPGAS.
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Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
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Reul, David A.; Raichle, Kurt R., Multi-vehicle communication interface.
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Taylor Brad (Oakland CA), Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication.
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Struhsaker Paul F. ; Hudson Thomas C., System for a base station for providing voice, data, and multimedia services in a wireless local loop system.
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Taylor Brad (Oakland CA) Dowling Robert (Albany CA), System for compiling algorithmic language source code for implementation in programmable hardware.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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연합인증

Integrated circuit having integrated programmable gate array and method of operating the same 원문보기

초록 ▼

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Integrated circuit having integrated programmable gate array and method of operating the same 원문보기

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이 특허에 인용된 특허 (17)

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