[특허]Temperature sensor scheme

Infineon Technologies AG

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특허 상세정보

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내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Temperature sensor scheme

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G01R-019/00 G01K-007/01 H05B-001/02
미국특허분류(USC)	702/064; 219/481; 219/497; 374/178; 374/183; 700/278
출원번호	US-0672246 (2003-09-25)
발명자 / 주소	Kim, Jung Pill
출원인 / 주소	Infineon Technologies AG
대리인 / 주소	Dicke, Billig &
인용정보	피인용 횟수 : 29 인용 특허 : 8

초록
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The present invention is a random access memory device including a temperature sensing circuit, and method of using the same. The temperature sensing circuit includes a first and a second comparator. Each comparator is configured to receive a sense voltage that is indicative of a sensed temperature. A first temperature reference circuit having a plurality of first reference voltages is coupled to the first comparator. The plurality of first reference voltages are alternately compared with the sense voltage. A second temperature reference circuit having a plurality of second reference voltages is coupled to the second comparator. The plurality of second reference voltages are alternately compared with the sense voltage. A first trimmer is coupled to the first temperature reference circuit. A second trimmer coupled to the second temperature reference circuit. The first and second trimmers are independently adjustable to adjust the plurality of first and second reference voltages.

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청구항
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1. A random access memory device including a temperature sensing circuit, the temperature sensing circuit comprising:a sensing device configured to hold a sensed voltage that varies with changes in temperature at the sensing device; a first comparator configured to receive the sensed voltage from the sensing device, the first comparator generating a first output signal; a second comparator configured to receive the sensed voltage from the sensing device, the second comparator generating a second output signal; a logic circuit configured to receive the first and second output signals; a first temperature reference circuit having a plurality of first reference voltages; a second temperature reference circuit having a plurality of second reference voltages; a first switch circuit coupled between the first temperature reference circuit and the first comparator, the first switch circuit controlled by the logic circuit such that a first reference voltage is applied to the first comparator; a second switch circuit coupled between the second temperature reference circuit and the second comparator, the second switch circuit controlled by the logic circuit such that a second reference voltage is applied to the second comparator; a first trimmer coupled to the first temperature reference circuit, the first trimmer being adjustable to adjust the first reference voltage; and a second trimmer coupled to the second temperature reference circuit, the second trimmer being adjustable to adjust the second reference voltage. 2. The random access memory device of claim 1 wherein the first trimmer is adjustable to correct for input offset voltage in the first comparator and the second trimmer is adjustable to correct for input offset voltage in the second comparator.3. The random access memory device of claim 1 wherein the first trimmer are resistors that are is adjustable to correct for input offset voltage in the first comparator and the second trimmer are resistors that are is adjustable to correct for input offset voltage in the second comparator.4. The random access memory device of claim 1 wherein the first and second trimmers are potentiometers that have adjustable resistance.5. The random access memory device of claim 1 wherein the first and second trimmers are multiple resistors that may be removed and added to the trimmers in order to provide adjustable resistance.6. A temperature sensing circuit comprising:a first and a second comparator each configured to receive a sense voltage that is indicative of a sensed temperature; a first temperature reference circuit having a plurality of first reference voltages coupled to the first comparator such that the plurality of first reference voltages are alternately compared with the sense voltage; a second temperature reference circuit having a plurality of second reference voltages coupled to the second comparator such that the plurality of second reference voltages are alternately compared with the sense voltage; a first trimmer coupled to the first temperature reference circuit and a second trimmer coupled to the second temperature reference circuit, the first and second trimmers being independently adjustable to adjust the plurality of first and second reference voltages; and wherein a first reference voltage compared to the sense voltage and a second reference voltage compared to the sense voltage are different from each other so that a determination is performed that the sensed temperature is in a range defined by the first reference voltage and the second reference voltage. 7. The temperature sensing circuit of claim 6 wherein the first trimmer is adjustable to correct for input offset voltage in the first comparator and the second trimmer is adjustable to correct for input offset voltage in the second comparator.8. The temperature sensing circuit of claim 6 wherein the first and second trimmers are resistors.9. The temperature sensing circuit of claim 6 wherein the first and second trimmers are potentiometers that have adjustable resistance.10. The temperature sensing circuit of claim 6 wherein the first and second trimmers are multiple resistors that may be removed and added to the trimmers in order to provide adjustable resistance.11. The temperature sensing circuit of claim 6 further including a sensing device configured to sense the sensed voltage that varies with changes in temperature at the sensing device.12. The temperature sensing circuit of claim 6 further including a logic circuit configured to receive a first output signal from the first comparator and a second output signals from the second comparator.13. The temperature sensing circuit of claim 12 further including a first switch circuit coupled between the first temperature reference circuit and the first comparator and a second switch circuit coupled between the second temperature reference circuit and the second comparator, the first and second switch circuits controlled by the logic circuit such that the plurality of first and second reference voltages are alternately compared with the sense voltage.14. The temperature sensing circuit of claim 6 configured to be integrated into a random access memory device.15. A method of decreasing current consumption in a dynamic memory device, the method including the steps of:providing a semiconductor memory device with a temperature sensing circuit; periodically refreshing the memory device at a refresh rate; sensing the temperature of the dynamic memory device with the temperature sensing circuit and producing a corresponding sensed temperature voltage; providing a first reference voltage; comparing the sensed temperature voltage with the first reference voltage using a first comparator with a first offset voltage; providing a second reference voltage; comparing the sensed temperature voltage with the second reference voltage using a second comparator with a second offset voltage; determining whether the sensed temperature voltage is within the first and second reference voltages; adjusting the first reference voltage to balance the first input offset voltage of the first comparator; and adjusting the second reference voltage to balance the second input offset voltage of the second comparator. 16. The method of claim 15 further including the step of adjusting the refresh rate based on whether sensed temperature voltage is between the first and second reference voltages.17. The method of claim 15 further including the step of decreasing the refresh rate when the sensed temperature voltage is between the first and second reference voltages.18. A random access memory device comprising:a first and a second comparator each configured to receive a sense voltage that is indicative of a sensed temperature; first means coupled to the first comparator for alternately comparing a plurality of first reference voltages with the sense voltage; second means coupled to the second comparator for alternately comparing a plurality of second reference voltages with the sense voltage; third means coupled to the first means for independently adjusting the plurality of first reference voltages; and fourth means coupled to the second means for independently adjusting the plurality of second reference voltages; and wherein a first reference voltage compared to the sense voltage and a second reference voltage compared to the sense voltage are different from each other so that a determination is performed that the sensed temperature is in a range defined by the first reference voltage and the second reference voltage. 19. The random access memory device of claim 18 wherein the third means are resistors that are adjustable to correct for input offset voltage in the first comparator and the fourth means are resistors that are adjustable to correct for input offset voltage in the second comparator.20. A random access memory device comprising:a first and a second comparator each configured to receive a sense voltage that is indicative of a sensed temperature; a first temperature reference circuit having a plurality of first reference voltages coupled to the first comparator such that the plurality of first reference voltages are alternately compared with the sense voltage; a second temperature reference circuit having a plurality of second reference voltages coupled to the second comparator such that the plurality of second reference voltages are alternately compared with the sense voltage; a first trimmer coupled to the first temperature reference circuit and a second trimmer coupled to the second temperature reference circuit, the first and second trimmers being independently adjustable to adjust the plurality of first and second reference voltages.

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이 특허를 인용한 특허 (29)

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Temperature sensor scheme

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이 특허에 인용된 특허 (8)

이 특허를 인용한 특허 (29)

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Temperature sensor scheme

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이 특허에 인용된 특허 (8)

이 특허를 인용한 특허 (29)

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IPC 상세정보(version : 201201)

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