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Contact capping local interconnect 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/44
출원번호 US-0632653 (2003-08-02)
발명자 / 주소
  • Geffken, Robert M.
  • Horak, David V.
  • Stamper, Anthony K.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Schmeiser, Olsen &
인용정보 피인용 횟수 : 10  인용 특허 : 24

초록

A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conductive wires/studs in the first insulative layer

대표청구항

1. An method for forming an electronic structure, comprising the steps of:providing a substrate layer that includes a first electronic device; forming a passivating layer on the substrate layer and in mechanic contact with the substrate layer, wherein the passivating layer is on the first electronic

이 특허에 인용된 특허 (24)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. Farooq Mukta Shaji ; Kaja Suryanarayana ; Perfecto Eric Daniel ; White George Eugene, Capped copper electrical interconnects.
  3. Uzoh Cyprian E., Continuous highly conductive metal wiring structures and method for fabricating the same.
  4. Izawa Tetsuo,JPX ; Goto Hiroshi,JPX ; Hashimoto Koichi,JPX, Enhanced semiconductor integrated circuit device with a memory array and a peripheral circuit.
  5. Klein Richard K. ; Selcuk Asim A. ; Kepler Nicholas J. ; Sander Craig S. ; Spence Christopher A. ; Lee Raymond T. ; Holst John C. ; Horne Stephen C., Forming local interconnects in integrated circuits.
  6. Wang Fei ; Holbrook Allison ; Kai James K., In-situ etch of BARC layer during formation of local interconnects.
  7. Huang Richard J. (Milpitas CA) Cheung Robin W. (Cupertino CA) Rakkhit Rajat (Milpitas CA) Lee Raymond T. (Sunnyvale CA), Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC applica.
  8. Wang Pailu ; Lien Chuen-Der ; Terrill Kyle W., Local interconnect structure and process for six-transistor SRAM cell.
  9. Sun Shih-Wei,TWX, Manufacturing method for self-aligned local interconnects and contacts simultaneously.
  10. Yen Ting P., Metal plug local interconnect.
  11. Adler Eric ; Trombley Henry W., Metal-insulator-metal capacitor for copper damascene process and method of forming the same.
  12. Kobeda Edward (Poughkeepsie NY) Patton Gary L. (Poughkeepsie NY), Method for fabricating bipolar and CMOS devices in integrated circuits using contact metallization for local interconnec.
  13. Furukawa Toshiharu ; Hakey Mark C. ; Holmes Steven J. ; Horak David V., Method for manufacturing a field effect transitor (FET) having mis-aligned-gate structure.
  14. Beasom James D. (Melbourne FL), Method of making trench conductor and crossunder architecture.
  15. Chen Hung-Sheng ; Kim Unsoon ; Sun Yu ; Chang Chi ; Ramsbey Mark ; Randolph Mark ; Kajita Tatsuya ; Hui Angela ; Wang Fei ; Chang Mark, Process for fabricating an integrated circuit with a self-aligned contact.
  16. Schinella Richard ; Sanganeria Mahesh K., Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate.
  17. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias.
  18. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD.
  19. Sullivan Timothy D., Semiconductor chip structures with embedded thermal conductors.
  20. Gardner Mark I. ; Kadosh Daniel ; Spikes ; Jr. Thomas E., Semiconductor fabrication employing a local interconnect.
  21. En William G. ; Ngo Minh Van ; Yang Chih-Yuh ; Foote David K. ; Bell Scott A. ; Karlsson Olov B. ; Lyons Christopher F., Silicon oxime spacer for preventing over-etching during local interconnect formation.
  22. Cheek Jon D. ; Wristers Derick J. ; Fulford H. Jim, Transistor formation with LI overetch immunity.
  23. Liaw Jhon-Jhy,TWX, Tungsten local interconnect, using a silicon nitride capped self-aligned contact process.
  24. Sullivan Timothy D., Upper redundant layer for damascene metallization.

이 특허를 인용한 특허 (10)

  1. Bonilla, Griselda; Choi, Samuel S. S.; Filippi, Ronald G.; Huang, Elbert E.; Lustig, Naftali E.; Simon, Andrew H., Alternate dual damascene method for forming interconnects.
  2. Summerfelt,Scott R.; Hall,Lindsey H.; Udayakumar,Kezhakkedath R.; Moise, IV,Theodore S., Ferroelectric capacitor stack etch cleaning methods.
  3. Oladeji, Isaiah O.; Cuthbertson, Alan, Method for fabricating a thick copper line and copper inductor resulting therefrom.
  4. Li, Hongqi; Jindal, Anurag; Vasilyeva, Irina, Methods of exposing conductive vias of semiconductor devices and associated structures.
  5. Lee,Kyoung Woo; Ku,Ja Hum; Hong,Duk Ho; Park,Wan Jae, Methods of forming integrated circuit devices having metal interconnect structures therein.
  6. Mehrotra,Manoj; Niimi,Hiroaki, Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices.
  7. Cabral, Jr., Cyril; Engelmann, Sebastian U.; Fletcher, Benjamin L.; Gordon, Michael S.; Joseph, Eric A., Patterning transition metals in integrated circuits.
  8. Cabral, Jr., Cyril; Engelmann, Sebastian U.; Fletcher, Benjamin L.; Gordon, Michael S.; Joseph, Eric A., Patterning transition metals in integrated circuits.
  9. Farooq, Mukta G.; Fasano, Benjamin V.; Frankel, Jason L.; Hamel, Harvey C.; Kadakia, Suresh D.; Long, David C.; Pompeo, Frank L.; Ray, Sudipta K., Structure for implementing secure multichip modules for encryption applications.
  10. Bao, Junjing; Bonilla, Griselda; Choi, Samuel S.; Filippi, Ronald G.; Lustig, Naftali E.; Simon, Andrew H., Subtractive etch interconnects.
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