초록 ▼

A structure is provided which suppresses a parasitic bipolar effect without decreasing the breakdown voltage at the junctions between the excessive carrier extracting region and source/drain regions of a MOS transistor for a voltage of approximately 15 volts in a semiconductor device formed on a sem

A structure is provided which suppresses a parasitic bipolar effect without decreasing the breakdown voltage at the junctions between the excessive carrier extracting region and source/drain regions of a MOS transistor for a voltage of approximately 15 volts in a semiconductor device formed on a semiconductor layer on an insulating layer. In the MOS transistor having a source tied body structure, a semiconductor regions having a low impurity concentration is formed between a regions for extracting excessive carriers and source/drain regions. Thus, the breakdown voltage at the junctions between the extracting regions and the source/drain regions is increased and a parasitic bipolar effect is suppressed without breakdown between the extracting regions and the source/drain regions.

대표청구항 ▼

1. A semiconductor device, comprising:a supporting substrate having insulation at least at a surface thereof; a semiconductor layer fanned on the surface of the supporting substrate; a transistor element fanned in the semiconductor layer, the transistor element comprising a channel region of a first

1. A semiconductor device, comprising:a supporting substrate having insulation at least at a surface thereof; a semiconductor layer fanned on the surface of the supporting substrate; a transistor element fanned in the semiconductor layer, the transistor element comprising a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an insulating layer formed on the channel region, and an electrode formed on the insulating layer; the transistor element including: a first semiconductor region of the first conductive type and a second semiconductor region of the first conductive type; the second semiconductor region being provided on the surface of the supporting substrate at least at one end, in a channel width direction, of at least one of the source region and the drain region, the second semiconductor region following the at least one end in a channel length direction; the electrode is non-overlapping with the second semiconductor region in plan view; the first semiconductor region being provided on the surface of the supporting substrate so as to be sandwiched by the second semiconductor region and one of the source region and the drain region, following the second semiconductor region; the second semiconductor region having an impurity concentration which is higher than that in the channel region, and the first semiconductor region being a semiconductor of the first conductive type, and having an impurity concentration which is higher than that in the channel region, and the first semiconductor region having an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region. 2. The semiconductor device according to claim 1, the first semiconductor region being a semiconductor of the first conductive type, and having an impurity concentration which is substantially the same as that in the channel region.3. The semiconductor device according to claim 1, the first semiconductor region substantially not being doped with an impurity.4. The semiconductor device according to claim 1, further comprising an LDD region of the second conductive type formed between the channel region and the source region and between the channel region and drain region, the first semiconductor region being a semiconductor of the first conductive type and having an impurity concentration which is substantially the same as that in an LDD region formed in a MOS transistor complementing a MOS transistor of a conductive type which is the same as that of the channel region.5. A semiconductor gate array, comprising:a supporting substrate having insulation at least at a surface thereof; a semiconductor layer formed on the surface of the supporting substrate; a plurality of transistor elements formed in the semiconductor layer, each of the transistor elements comprising a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an insulating layer formed on the channel region, and an electrode formed on the insulating layer, a first semiconductor region provided on the surface of the supporting substrate at least at one end in a channel width direction of at least one of the source region and the drain region along a channel length direction; a second semiconductor region of the first conductive type provided on the surface of the supporting substrate so as to sandwich the first semiconductor region by the source region or the drain region along the first semiconductor region, the second semiconductor region having an impurity concentration which is higher than that in the channel region, and the first semiconductor region having an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region; and the electrode is non-overlapping with the second semiconductor region in plan view. 6. The semiconductor gate array according to claim 5, the first semiconductor region of each MOS transistor being a semiconductor of the first conductive type, and having an impurity concentration which is lower than that in the second semiconductor region.7. The semiconductor gate array according to claim 5, the first semiconductor region of each MOS transistor being a semiconductor of the first conductive type, and having an impurity concentration which is substantially the same as that in the channel region.8. The semiconductor gate array according to claim 5, the first semiconductor region of each MOS transistor substantially not being doped with an impurity.9. The semiconductor gate array according to claim 5, further comprising an LDD region of the second conductive type formed between the channel region and the source region and between the channel region and drain region, the first semiconductor region of each MOS transistor being a semiconductor of the first conductive type and having an impurity concentration which is substantially the same as that in an LDD region formed in a MOS transistor complementing a MOS transistor of the conductive type which is the same as that of a channel region.10. A semiconductor device, comprising:a supporting substrate having insulation at least at a surface thereof; a semiconductor layer formed on the surface of the supporting substrate; a plurality of transistor elements formed in the semiconductor layer and connected to each other in series, each of the transistor elements comprising a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an insulating layer formed on the channel region, and an electrode formed on the insulating layer; a first semiconductor region provided on the surface of the supporting substrate at least at one end in a channel width direction of one of source region and the drain region among source regions and drain regions of respective MOS transistors along a channel length direction, which is not directly connected to an electrical power source; a second semiconductor region of the first conductive type provided on the surface of the supporting substrate so as to sandwich the first semiconductor region by the source region or the drain region along the first semiconductor region; the electrode is non-overlapping with the second semiconductor region in plan view; and a third semiconductor region of the first conductive type provided on the surface of the supporting substrate at least at one end in the channel width direction of one of the source region and the drain region along the source region and the drain region, which is directly connected to the electrical power source, each of the second semiconductor region and the third semiconductor region having an impurity concentration which is higher than that in the channel region, and the first semiconductor region having an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region. 11. The semiconductor device according to claim 10, the first semiconductor region being a semiconductor of the second conductive type, and having an impurity concentration which is lower than that in the source region and the drain region.12. The semiconductor device according to claim 10, the first semiconductor region being a semiconductor of the first conductive type, and having an impurity concentration which is lower than that in the second semiconductor region.13. The semiconductor device according to claim 10, the first semiconductor region being a semiconductor of the first conductive type, and having an impurity concentration which is substantially the same as that in the channel region.14. The semiconductor device according to claim 10, the first semiconductor region substantially not being doped with an impurity.15. The semiconductor device according to claim 10, further comprising an LDD region of the second conductive type formed between the channel region and the source region and between the channel region and drain region, the first semiconductor region being a semiconductor of the second conductive type and having an impurity concentration which is substantially the same as that in the LDD region.16. The semiconductor device according to claim 10, further comprising an LDD region of the second conductive type formed between the channel region and the source region and between the channel region and drain region, and first semiconductor region being a semiconductor of the first conductive type and having an impurity concentration which is substantially the same as that in an LDD region formed in a MOS transistor complementing a MOS transistor of the conductive type which is the same as that of the channel region.17. The semiconductor device according to claim 10, the supporting substrate having insulation at least at a surface thereof comprising a base substrate and an insulating layer formed on the base substrate.18. The semiconductor device according to claim 17, the base substrate comprising single-crystal silicon.19. The semiconductor device according to claim 17, the base substrate comprising quartz, and the semiconductor layer formed on the insulating layer of the supporting substrate comprising single-crystal silicon.20. The semiconductor device according to claim 17, the base substrate comprising quartz, and the semiconductor layer formed on the insulating layer of the supporting substrate comprising polycrystalline silicon.21. The semiconductor device according to claim 17, the base substrate comprising glass.22. A semiconductor device according to claim 10, further comprising a contact line provided over and electrically connected to grounded source regions, among the source regions and the drain regions of the plurality of MOS transistors which are connected to each other in series, and the first semiconductor regions being adjacent to the grounded source regions.23. An electro-optical device, comprising:the supporting substrate constituting the semiconductor device according to claim 10 as a first support substrate; a second supporting substrate facing the semiconductor layer formed on the insulating layer on the first supporting substrate; and a liquid crystal disposed between the first supporting substrate and the second supporting substrate, and driven by transistor elements in the semiconductor layer. 24. An electronic equipment, comprising:a light source; the electro-optical device according to claim 23 that modulates light incident on the light source in response to image information; and a projection device that projects the light modulated by the electro-optical device.