Architecture that converts a half-duplex bus to a full-duplex bus while keeping the bandwidth of the bus constant
IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0915794
(2001-07-26)
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발명자
/ 주소 |
- Li, Gabriel
- Grivna, Edward L.
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출원인 / 주소 |
- Cypress Semiconductor Corp.
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대리인 / 주소 |
Christopher P. Maiorana, PC
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인용정보 |
피인용 횟수 :
7 인용 특허 :
5 |
초록
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An architecture comprising a first circuit, a second circuit, and one or more pairs of communication channels. The first circuit may be configured to transmit one or more first serial streams in response to a plurality of first source data streams and recover a plurality of second source data stream
An architecture comprising a first circuit, a second circuit, and one or more pairs of communication channels. The first circuit may be configured to transmit one or more first serial streams in response to a plurality of first source data streams and recover a plurality of second source data streams from one or more second serial streams. The second circuit may be configured to transmit the one or more second serial streams in response to the plurality of second source data streams and recover the plurality of first source data streams in response to the one or more first serial streams. The first circuit and the second circuit may be coupled by the one or more pairs of communication channels. The first and second circuits may be configured to transmit simultaneously.
대표청구항
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1. An architecture comprising:a first circuit configured to (i) transmit one or more first serial streams in response to a plurality of first source data streams and (ii) recover a plurality of second source data streams in response to one or more second serial streams; a second circuit configured t
1. An architecture comprising:a first circuit configured to (i) transmit one or more first serial streams in response to a plurality of first source data streams and (ii) recover a plurality of second source data streams in response to one or more second serial streams; a second circuit configured to (i) transmit said one or more second serial streams in response to said plurality of second source data streams and (ii) recover said plurality of first source data streams in response to said one or more first serial streams; and one or more pairs of communication channels coupling said first circuit and said second circuit, wherein (i) each of said first and second serial streams comprise interleaved data from said first and second source data streams, respectively and (ii) said first and second circuits are configured to transmit simultaneously. 2. The architecture according to claim 1, wherein:said first circuit is further configured to transmit via a first communication channel of each of said one or more pairs of communication channels; and said second circuit is further configured to transmit via a second communication channel of each of said one or more pairs of communication channels. 3. The architecture according to claim 2, wherein the number of serial streams is less than the number of source streams.4. The architecture according to claim 1, wherein said serial streams have a signaling rate that is an integer multiple of a data rate of said source data streams.5. The architecture according to claim 1, wherein each of said communication channels comprises a simplex serial link comprising a transmission line selected from the group consisting of a fiber optic cable, a coaxial cable, a twisted pair cable, a microstrip transmission line, a stripline transmission line, and any other transmission line configured to carry said serial stream.6. The apparatus according to claim 1, wherein:said first and second circuits are further configured to convert said one or more pairs of communication channels from half-duplex operation to full-duplex operation while maintaining a bandwidth of said one or more pairs of communication channels. 7. An apparatus comprising:a first circuit configured to generate one or more first interleaved streams in response to a plurality of first source data streams; and a second circuit configured to recover a plurality of second source data streams in response to one or more second interleaved data streams. 8. The apparatus according to claim 7, wherein said one or more first interleaved data streams are carried by a first communication channel of each of one or more pairs of communication channels.9. The apparatus according to claim 8, wherein said one or more second interleaved data streams are carried by a second communication channel of each of said one or more pairs of communication channels.10. The apparatus according to claim 7, wherein said first circuit comprises an interleaver circuit configured to multiplex said plurality of first source data streams into said one or more first interleaved data streams.11. The apparatus according to claim 7, wherein said second circuit comprises a bonding circuit configured to generate one or more bonded (aligned) data streams from said one or more second interleaved data streams.12. The apparatus according to claim 11, wherein said second circuit further comprises a de-interleaver circuit configured to demultiplex said plurality of second source data streams from said one or more bonded data streams.13. The apparatus according to claim 7, wherein said serial streams have a signaling rate that is an integer multiple of a data rate of said source data streams.14. The apparatus according to claim 13, wherein said integer multiple is equal to the product of a number of source data streams carried by an interleaved data stream and a parallel-to-serial conversion ratio used to generate said serial stream from said interleaved data stream.15. The apparatus according to claim 7, wherein each of said one or more serial streams are carried by a communication channel comprising one or more simplex serial links comprising a transmission line selected from the group consisting of a fiber optic cable, a coaxial cable, a twisted pair cable, a microstrip transmission line, a stripline transmission line, and any other transmission line configured to carry said serial stream.16. A method for multiplying a throughput of one or more pairs of communication channels comprising the steps of:(A) communicating a plurality of first source data streams from a first host to a second host as one or more first interleaved data streams via a first communication channel of each of said one or more pairs of communication channels; and (B) communicating a plurality of second source data streams from said second host to said first host as one or more second interleaved data streams via a second communication channel of each of said one or more pairs of communication channels. 17. The method according to claim 16, wherein the step A and the step B are performed simultaneously.18. The method according to claim 16, wherein the step A comprises the sub-steps of:generating one or more first serial streams in response to said plurality of first source data streams; and recovering said plurality of first source data streams from said one or more first serial streams. 19. The method according to claim 16, wherein the step B comprises the sub-steps of:generating one or more second serial streams in response to said plurality of second source data streams; and recovering said plurality of second source data streams from said one or more second serial streams. 20. The method according to claim 16, wherein said interleaved data streams are serialized to generate serial streams.21. The method according to claim 20, wherein said source data streams are recovered by deserializing, bonding and de-interleaving said serial streams.22. The method according to claim 16, further comprising the step of:converting said one or more pairs of communication channels from half-duplex operation at a first rate to full-duplex operation at a second rate, wherein said second rate is set to maintain a bandwidth of said one or more pairs of communication channels at said first rate. 23. The apparatus according to claim 6, wherein:said first and second circuits are further configured to connect to said one or more pairs of communication channels in place of input and output buffers arranged as bi-directional bus drivers.
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