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Conductive container structures having a dielectric cap 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/20
  • H01L-021/8242
출원번호 US-0945397 (2001-08-30)
발명자 / 주소
  • Sandhu, Gurtej Singh
  • Reinberg, Alan R.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner &
인용정보 피인용 횟수 : 4  인용 특허 : 84

초록

Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjac

대표청구항

1. A method of forming a semiconductor structure, comprising:forming an insulating layer on a substrate; forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer; forming a conductive layer on th

이 특허에 인용된 특허 (84)

  1. Havens Marvin R. (Greer SC) Wilkie Robert R. (Roanoke Rapids NC), Antistatic/conductive container.
  2. Sandhu Gurtej S. (Boise ID) Fazan Pierre C. (Boise ID), Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for fo.
  3. Fazan Pierre C. (Boise ID) Sandhu Gurtej S. (Boise ID), Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for.
  4. Pan Pai-Hung, Container-shaped bottom electrode for integrated circuit capacitor with partially rugged surface.
  5. Kim Yun-Gi,KRX, Cylindrical capacitor and method for fabricating same.
  6. Fazan Pierre C. (Boise ID) Lee Ruojia R. (Boise ID), DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance.
  7. Figura Thomas A. ; Wu Zhiquiang ; Li Li, Doped silicon structure with impression image on opposing roughened surfaces.
  8. Popp Franz-Wolfgang (Wedemark DEX) Pontani Bernd (Alzenau DEX) Ernst Erich (Oftersheim DEX), Double container system for transporting and storing radioactive materials.
  9. Fazan Pierre (Boise ID) Sandhu Gurtej S. (Boise ID), Dram cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for a capacitive surfac.
  10. Hieda Katsuhiko (Yokohama JPX) Nitayama Akihiro (Kawasaki JPX) Horiguchi Fumio (Tokyo JPX), Dynamic ram, having an improved large capacitance.
  11. Wu Der-Yuan,TWX ; Jenq Jason,TWX, Fabricating method of dynamic random access memory.
  12. Lin Dahcheng,TWX ; Chang Jung-Ho,TWX ; Chen Hsi-Chuan,TWX ; Tseng Kuo-Shu,TWX, Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications.
  13. Sandhu Gurtej S. ; Rolfson J. Brett, Integrated capacitor bottom electrode for use with conformal dielectric.
  14. Sandhu Gurtej S. (Boise ID), Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance.
  15. Green James E., Method for constructing multiple container capacitor.
  16. Jun Young K. (Seoul KRX), Method for fabricating a capacitor cell in the semiconductor memory device having a step portion.
  17. Jenq J. S. Jason,TWX ; Chien Sun-Chieh,TWX ; Wu Der-Yuan,TWX ; Wang Chuan-Fu,TWX, Method for fabricating a cylinder capacitor.
  18. Koh Chao-Ming (Hsinchu TWX), Method for fabricating a stacked capacitor with a self aligned node contact in a memory cell.
  19. Cho Bok-Won,KRX, Method for fabricating capacitor of semiconductor device using hemispherical grain (HSG) polysilicon.
  20. Liaw Ing-Ruey (Hsinchu TWX) Cherng Meng-Jaw (Hsinchu TWX), Method for fabricating crown capacitors for a dram cell.
  21. Watanabe Hirohito (Tokyo JPX) Tatsumi Toru (Tokyo JPX), Method for fabricating polycrystalline silicon having micro roughness on the surface.
  22. Woo Sang Ho (Bubaleub KRX), Method for fabricating storage electrode of semiconductor device.
  23. Harris ; Erik Preston ; Keyes ; Robert William, Method for fabricating ultra-narrow metallic lines.
  24. Robb Francine Y. (Tempe AZ) Robinson F. J. (Scottsdale AZ) Svechovsky Bridget (Phoenix AZ) Wood Thomas E. (Chandler AZ), Method for filling trenches from a seed layer.
  25. Dennison Charles H. (Boise ID) Chan Hiang (Boise ID) Liu Yauh-Ching (Boise ID) Fazan Pierre (Boise ID) Rhodes Howard E. (Boise ID), Method for formation of a stacked capacitor.
  26. Fazan Pierre C. (Boise ID), Method for forming a storage cell capacitor compatible with high dielectric constant materials.
  27. Sandhu Gurtej S. (Boise ID) Fazan Pierre C. (Boise ID), Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer.
  28. Lin Kuen-Yow,TWX ; Chern Horng-Nan,TWX, Method for forming capacitor of memory cell.
  29. Chu Jack C. (Long Island City NY) Hsu Louis Lu-Chen (New York NY) Mii Toshio (Essex Junction VT) Shepard Joseph F. (Hopewell Junction NY) Stiffler Scott R. (Brooklyn NY) Tejwani Manu J. (Yorktown Hei, Method for forming capacitors with roughened single crystal plates.
  30. Dennison Charles H. (Boise ID) Thakur Randhir P. S. (Boise ID), Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon.
  31. Weimer Ronald A. (Boise ID) Thakur Randhir P. S. (Boise ID) Kepten Avishai (Migdal Haemek ILX) Sendler Michael (Migdal Haemek ILX), Method for forming hemispherical grained silicon.
  32. Sandhu Gurtej Singh ; Thakur Randhir P.S., Method for making a container capacitor with increased surface area.
  33. Chen Li Yeat,TWX, Method for making dynamic random access memory cells having brush-shaped stacked capacitors patterned from a hemispherical grain hard mask.
  34. Han Ki-man (Kyungki KRX) Hwang Chang-gyu (Seoul KRX) Kang Dug-dong (Kyungki KRX) Choi Young-Jae (Kyungki KRX) Yoon Joo-young (Kyungki KRX), Method for manufacturing a capacitor of a semiconductor device.
  35. Park Young-woo (Kyungi-do KRX) No Jun-yong (Incheon KRX) Sim Sang-pil (Suwon KRX), Method for manufacturing a semiconductor memory device having a capacitor with increased effective area.
  36. Yang Fu-Liang,TWX ; Jeng Erik S.,TWX, Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory.
  37. Tuan Hsiao-Chin (Hsin-Chu TWX) Chou Hsiang-Ming J. (Hsin-Chu TWX), Method for producing a roughened surface capacitor.
  38. Reinberg Alan R. (Westport CT) Rhodes Howard E. (Boise ID), Method of creating sharp points and other features on the surface of a semiconductor substrate.
  39. Tseng Horng-Huei (Hsin-Chu TWX) Lu Chih-Yuan (Hsin-Chu TWX), Method of forming a DRAM stack capacitor with ladder storage node.
  40. Dennison Charles (Boise ID), Method of forming a bit line over capacitor array of memory cells.
  41. Akram Salman (Boise ID) Turner Charles (Chandler AZ) Laulusa Alan (Boise ID), Method of forming a capacitor.
  42. Fischer Mark (Boise ID) Jost Mark (Boise ID) Parekh Kunal (Boise ID), Method of forming a cylindrical container stacked capacitor.
  43. Weimer Ronald A. ; Thakur Randhir P. S. ; Kepten Avishai,ILX ; Sendler Michael,ILX, Method of forming hemispherical grained silicon.
  44. Dennison Charles H. ; Howard Bradley J. ; Jost Mark E., Method of forming recessed container cells.
  45. Cathey David A. (Boise ID) Tuttle Mark E. (Boise ID) Lowrey Tyler A. (Boise ID), Method of increasing capacitance by surface roughening in semiconductor wafer processing.
  46. Sharan Sujit ; Figura Thomas A. ; Srinivasan Anand ; Sandhu Gurtej S., Method of increasing capacitance of memory cells incorporating hemispherical grained silicon.
  47. Figura Thomas A. ; Wu Zhiquiang ; Li Li, Method of making a doped silicon structure with impression image on opposing roughened surfaces.
  48. Ahn Ji-hong (Seoul KRX), Method of making a semiconductor memory device having improved electrical characteristics.
  49. Noble ; Jr. Wendell P. (84 Swamp Rd. Milton VT 05468), Method of making a trench capacitor field shield with sidewall contact.
  50. Green James E. ; Clampitt Darwin, Method of making capacitor and conductive line constructions.
  51. Birritella Mark S. (Phoenix AZ) McLaughlin Kevin (Chandler AZ), Method of making closely spaced contacts to PN-junction using stacked polysilicon layers, differential etching and ion i.
  52. Sandhu Gurtej S. ; Roberts Ceredig, Method of making straight wall containers and the resultant containers.
  53. Lee Jin H. (Daejeon KRX) Kim Cheon S. (Daejeon KRX) Lee Kyu H. (Daejeon KRX) Kim Dae Y. (Daejeon KRX), Method of manufacturing DRAM cell having a cup shaped polysilicon storage electrode.
  54. Cho Jaeshin (Gilbert AZ), Method of manufacturing a III-V semiconductor gate structure.
  55. Sugahara Kazuyuki (Hyogo JPX) Arima Hideaki (Hyogo JPX), Method of manufacturing semiconductor device having a capacitor.
  56. Wu Shye-Lin (Hsinchu TWX), Method to form a capacitor having multiple pillars for advanced DRAMS.
  57. Thakur Randhir P. S. (Boise ID) Nuttall Michael (Meridian ID), Method to form hemispherical grain (HSG) silicon by implant seeding followed by vacuum anneal.
  58. Thakur Randhir P. S. (Boise ID), Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal.
  59. Thakur Randhir P. S. (Boise ID), Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal.
  60. Yoo Chue-San,TWX ; Wang Chen Jong,TWX ; Chiang Wen Chuan,TWX, Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure.
  61. Dennison Charles H. (Meridian ID) Thakur Randhir P. S. (Boise ID), Method to thermally form hemispherical grain (HSG) silicon to enhance capacitance for application in high density DRAMs.
  62. Kim Tae-sung,KRX, Methods for fabricating microelectronic capacitor structures.
  63. Parekh Kunal R. ; Zahurak John K. ; Wald Phillip G., Methods of forming capacitors DRAM arrays, and monolithic integrated circuits.
  64. Park In-sung,KRX ; Kim Kyung-hoon,KRX, Microelectronic capacitors having tantalum pentoxide dielectrics and oxygen barriers.
  65. Dennison Charles H. (Boise ID), Multi-pin stacked capacitor utilizing micro villus patterning in a container cell and method to fabricate same.
  66. Li Weimin ; Sandhu Gurtej S., Multiple step methods for forming conformal layers.
  67. Li Weimin ; Sandhu Gurtej S., Multiple step methods for forming conformal layers.
  68. Fazan Pierre C. (Boise ID) Figura Thomas A. (Boise ID), Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack.
  69. Brown Kris K. (Garden City ID), Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon.
  70. Batra Shubneesh ; Fazan Pierre C. ; Zahurak John K., Process for improving roughness of conductive layer.
  71. Fazan Pierre (Boise ID) Mathews Viju (Boise ID), Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node.
  72. Thakur Randhir P. S. ; Pan James, Selective deposition of amorphous silicon film seeded in a chlorine gas and a hydride gas ambient when forming a stacked capacitor with HSG.
  73. Tseng Horng-Huei (Hsinchu TWX), Self-aligned cylindrical stacked capacitor DRAM cell.
  74. Ogawa Toshiaki (Hyogo JPX), Semiconductor memory device having a capacitor.
  75. Hidaka Hideto,JPX ; Tsuruda Takahiro,JPX ; Suma Katsuhiro,JPX, Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions.
  76. Dennison Charles H. (Boise ID) Walker Michael A. (Boise ID), Semiconductor processing methods of forming stacked capacitors.
  77. Abernathey John R. (Essex VT) Johnson David L. (Jericho VT) Pan Pai-Hung (Essex Junction VT) Paquette Charles A. (Saint Albans VT), Silicon oxynitride storage node dielectric.
  78. Clampitt Darwin A., Spacer patterned, high dielectric constant capacitor.
  79. Dennison Charles H. (Meridian ID) Ahmad Aftab (Boise ID), Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells.
  80. Wakamiya Wataru (Hyogo JPX) Tanaka Yoshinori (Hyogo JPX) Eimori Takahisa (Hyogo JPX) Ozaki Hiroji (Hyogo JPX) Kimura Hiroshi (Hyogo JPX) Satoh Shinichi (Hyogo JPX), Stacked capacitor type semiconductor memory device and manufacturing method thereof.
  81. Hayashide Yoshio (Hyogo JPX) Wakamiya Wataru (Hyogo JPX), Stacked type capacitor having a dielectric film formed on a rough surface of an electrode and method of manufacturing th.
  82. Brown Kris K. (Garden City ID), Storage capacitor structures using CVD tin on hemispherical grain silicon.
  83. Wen Duen-Shun (Crompond NY), Textured polysilicon stacked trench capacitor.
  84. Lur Water (Taipei TWX) Huang Cheng-Han (Hsin-chu TWX) Chang Shih-Chanh (Taichung TWX) Lin Liang-Chih (Hsin-chu TWX), Tungsten-plug process.

이 특허를 인용한 특허 (4)

  1. Sandhu,Gurtej Singh; Reinberg,Alan R., Conductive container structures having a dielectric cap.
  2. Sandhu,Gurtej Singh; Reinberg,Alan R., Conductive container structures having a dielectric cap.
  3. Thies,Andreas; Muemmler,Klaus, Method of manufacturing a semiconductor device.
  4. Kang, Kyong-Rim; Ahn, Sun-Yul; Kim, Young-Ho; Kim, Jae-Hyun; Yang, Joo-Hyung; Kim, Tae-Sung, Polymer resin composition, related method for forming a pattern, and related method for fabricating a capacitor.
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