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Method and system for dynamic power supply voltage adjustment for a semiconductor integrated circuit device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01K-001/00
출원번호 US-0078292 (2002-02-15)
발명자 / 주소
  • Mimberg, Ludger
  • Wagner, Barry
  • Lao, Mau
출원인 / 주소
  • nVIDIA Corporation
대리인 / 주소
    Wagner, Murabito &
인용정보 피인용 횟수 : 50  인용 특허 : 6

초록

A processor power supply voltage controller. The controller includes a temperature sensor configured to sense a temperature of a processor and generate a temperature signal in accordance therewith. A regulator is coupled to provide a power supply voltage to the processor. The regulator is coupled to

대표청구항

1. A processor power supply voltage controller comprising:a temperature sensor configured to sense a temperature of a processor and generate a temperature signal in accordance therewith; anda regulator coupled to provide a power supply voltage to the processor, the regulator coupled to receive the t

이 특허에 인용된 특허 (6)

  1. Reinhardt Dennis ; Bhat Ketan ; Jackson Robert T. ; Senyk Borys ; Matter Eugene P. ; Gunther Stephen H., Apparatus and method for controlling power usage.
  2. Patel Rakesh H. ; Turner John E. ; Lam John D. ; Wong Wilson, Circuitry for a low internal voltage integrated circuit.
  3. Gerald Talbot ; Michael J. Osborn ; Mark D. Hummel, Low voltage differential receiver/transmitter and calibration method thereof.
  4. Brown Alan E. (Georgetown TX), Over temperature memory circuit.
  5. Hunsdorf Jon ; Pellock ; III Charles ; Landfried David, Temperature and current dependent regulated voltage source.
  6. Bausch James F. ; Van Brocklin Andrew L. ; Stryker Chadwick W., Voltage control of integrated circuits.

이 특허를 인용한 특허 (50)

  1. Kolinummi, Pasi; Nokkonen, Erkki; Jager, Mike, Adaptive voltage adjustment.
  2. Hamann, Hendrik F.; Iyengar, Madhusudan K.; Lacey, James A.; Schmidt, Roger R., Apparatus for thermal characterization under non-uniform heat load.
  3. Hamann, Hendrik F.; Iyengar, Madhusudan K.; Lacey, James A.; Schmidt, Roger R., Apparatus for thermal characterization under non-uniform heat load.
  4. Hamann, Hendrik F.; Iyengar, Madhusudan K.; Lacey, James A.; Schmidt, Roger R., Apparatus for thermal characterization under non-uniform heat load.
  5. Bakalash, Reuven; Leviathan, Yaniv, Computing system having multi-mode parallel graphics rendering subsystem (MMPGRS) employing real-time automatic scene profiling and mode control.
  6. Su, Chih-Heng; Chen, Chih-Yuan; Li, Ciou-Fong, Dynamic voltage adjustment device and power transmission system using the same.
  7. Bakalash, Reuven; Leviathan, Yaniv, Game console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console board.
  8. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus.
  9. Bakalash, Reuven; Remez, Offir; Fogel, Efi, Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction.
  10. Cornwell, Michael J.; Dudte, Christopher P.; Wakrat, Nir Jacob, Initiating memory wear leveling.
  11. Rakshani, Vafa James; Krishnan, Musaravakkam Samaram, Integrated circuit with modular dynamic power optimization architecture.
  12. Bakalash, Reuven; Leviathan, Yaniv, Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications.
  13. Bakalash, Reuven; Shoshan, Yoel; Sela, Guy, Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications.
  14. Reddy, Sreenivas Aerra; Arulanandam, Srinivasan; Rajaraman, Venkataraman, Maintaining optimum voltage supply to match performance of an integrated circuit.
  15. Wagner, Barry A., Management of operation of an integrated circuit.
  16. White, Jonathan B.; van Welzen, James L., Method and apparatus for adaptive power consumption.
  17. Huang, Jensen; Diard, Franck; Saulters, Scott, Method and system for artificially and dynamically limiting the framerate of a graphics processing unit.
  18. Rozas, Guillermo J., Method and system for automatically calibrating intra-cycle timing relationships for sampling signals for an integrated circuit device.
  19. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system.
  20. Remez, Offir, Method of dynamic load-balancing within a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization.
  21. Bakalash, Reuven; Leviathan, Yaniv, Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations.
  22. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, Method of providing a PC-based computing system with parallel graphics processing capabilities.
  23. Diard, Franck; Kadaba, Ganesh, Methods and system for artifically and dynamically limiting the display resolution of an application.
  24. Cornwell, Michael J.; Dudte, Christopher P., Monitoring health of non-volatile memory.
  25. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus.
  26. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics application.
  27. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application.
  28. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application.
  29. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation.
  30. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation.
  31. Bakalash, Reuven; Remez, Offir; Bar-Or, Gigy; Fogel, Efi; Shaham, Amir, PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router.
  32. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications.
  33. Bakalash, Reuven; Remez, Offir; Fogel, Efi, PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics application.
  34. Bakalash, Reuven; Leviathan, Yaniv, PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications.
  35. Bakalash, Reuven; Leviathan, Yaniv, Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS.
  36. Li, Sau Yan Keith; Dewey, Thomas Edward; Jamkar, Saket Arun; Parikh, Amit, Power consumption reduction systems and methods.
  37. Sawyers, Thomas P.; Carroll, Barry N., Power delivery systems and methods.
  38. Frid, Aleksandr; Sriram, Parthasarathy, Power management with dynamic frequency adjustments.
  39. Frid, Aleksandr; Sriram, Parthasarathy, Power management with dynamic frequency adjustments.
  40. Kelleher, Brian M.; Mimberg, Ludger; Kranzusch, Kevin; Lam, John; Velmurugan, Senthil S., Processor performance adjustment system and method.
  41. Alben, Jonah M.; Kranzusch, Kevin, Processor temperature adjustment system and method.
  42. Alben, Jonah M.; Kranzusch, Kevin, Processor voltage adjustment system and method.
  43. Wyatt, David, Regulating power using a fuzzy logic control system.
  44. Wyatt, David, Regulating power within a shared budget.
  45. Cornwell, Michael J.; Dudte, Christopher P.; Fisher, Jr., Joseph R., Reporting flash memory operating voltages.
  46. Cornwell, Michael J.; Dudte, Christopher P.; Fisher, Jr., Joseph R., Reporting flash memory operating voltages.
  47. Bakalash, Reuven; Remez, Offir; Fogel, Efi, Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem.
  48. Remez, Offir; Shoshan, Yoel; Sela, Guy, Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem.
  49. Riedlinger, Reid J.; Liepe, Steven F.; Cutter, Douglas John, System and method for adjusting operating points of a processor based on detected processor errors.
  50. Cornwell, Michael J.; Dudte, Christopher P.; Wakrat, Nir Jacob, Updating error correction codes for data blocks.
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