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Tool suite for the rapid development of advanced standard cell libraries employing the connection properties of nets to identify potential pin placements 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0366463 (2003-02-14)
발명자 / 주소
  • Brown, III, Arnett J.
  • Stalker, Robert J.
  • Lakhani, Rajen Naran
  • Neiderer, Eric Wayne
  • Bayles, Devin
출원인 / 주소
  • BAE Systems and Information and Electronic Integration, Inc.
대리인 / 주소
    Swidler Berlin LLP
인용정보 피인용 횟수 : 17  인용 특허 : 14

초록

A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool suite may include a post operations tool, an audit tool, a custom interface, a setup file and a place and

대표청구항

1. A method of defining a cell to a routing tool, comprising:providing a cell abstract comprising design parameters describing the cell to a placement and wiring tool, the design parameters including nets; modifying a designation representing a strength of connection between potential pin placements

이 특허에 인용된 특허 (14)

  1. Tommy K. Eng, Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information.
  2. Bamji Cyrus (Fremont CA) Varadarajan Ravi (Fremont CA), Hier archical pitchmaking compaction method and system for integrated circuit design.
  3. Heimlich Michael C. ; St. Hilaire Kenneth R., Hierarchical adaptive state machine for emulating and augmenting software.
  4. Bamji Cyrus (Fremont CA) Varadarajan Ravi (Fremont CA), Identifying overconstraints using port abstraction graphs.
  5. Takahashi Naoya (Tokyo JPX), Integrated circuit and layout system therefor.
  6. Jones Larry G. (Austin TX) Blaauw David T. (Austin TX) Maziasz Robert L. (Austin TX) Guruswamy Mohan (Austin TX), Method and apparatus for designing an integrated circuit.
  7. Raad George B. ; Casper Stephen L., Method and memory device for dynamic cell plate sensing with ac equilibrate.
  8. Nishiyama Tamotsu (Hirakata JPX) Ikeda Kazushi (Tsu JPX) Matsunaga Tomoko (Kumamoto JPX), Method of and system for automatically generating network diagrams.
  9. Gould Elliot L. (Colchester VT) Kemerer Douglas W. (Essex Junction VT) McAllister Lance A. (Williston VT) Piro Ronald A. (South Burlington VT) Richardson Guy R. (Milton VT) Wellburn Deborah A. (Colch, Method of combining gate array and standard cell circuits on a common semiconductor chip.
  10. Groeneveld Patrick R. ; van Ginneken Lukas P. P. P., Method of designing a constraint-driven integrated circuit layout.
  11. Tomita Yasuhiro (Hyogo JPX), Net list for use in logic simulation and back annotation method of feedbacking delay information obtained through layout.
  12. Matsumoto Nobu (Kanagawa-ken JPX), Semiconductor element layout method employing process migration.
  13. Brown, III, Arnett J.; Stalker, Robert J.; Lakhani, Rajen Naran; Neiderer, Eric Wayne; Bayles, Devin, Tool suite for the rapid development of advanced standard cell libraries.
  14. Bamji Cyrus (Fremont CA) Varadarajan Ravi (Fremont CA), Virtual interface representation of hierarchical symbolic layouts.

이 특허를 인용한 특허 (17)

  1. Ito,Takeshi; Ikeda,Takahiro; Hashimoto,Koji, Apparatus and method for verifying an integrated circuit pattern.
  2. Andreev,Alexander E.; Pavisic,Ivan; Bolotov,Anatoli, Compact custom layout for RRAM column controller.
  3. Alpert, Charles J.; Huber, Andrew D.; Li, Zhuo; Nam, Gi-Joon; Ramji, Shyam; Roy, Jarrod A.; Taghavi, Taraneh E.; Tellez, Gustavo E.; Villarrubia, Paul G.; Viswanathan, Natarajan, Detailed routability by cell placement.
  4. Qian, Qi-De, Integrated circuits having in-situ constraints.
  5. Akselrod, Arkady; Kelkar, Sameer; Starr, Timothy E. W., Method and apparatus for design of a power supply.
  6. Goyal,Saket K., Method and system of generic implementation of sharing test pins with I/O cells.
  7. Woods, Wayne H.; Zemke, Cole E., Method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models.
  8. Perry,Jeffrey Robert; Garrison,Martin; Nguyen,Khang; Levin,Richard; Garrett,Wanda Carol; Gibson,Phillip; Lee,Benjamin H., Method for creating, modifying, and simulating electrical circuits over the internet.
  9. Nation,George W.; Lippert,Gary; Delp,Gary S., Method for generalizing design attributes in a design capture environment.
  10. Corbeil, Jr.,John D.; Saunders,Michael J., Method for performing design rule check of integrated circuit.
  11. Alley,Charles L.; Likovich, Jr.,Robert B.; Mendenhall,Joseph D.; Winemiller,Chad E., Methods and readable media for using relative positioning in structures with dynamic ranges.
  12. Song, Taejoong; Baek, Sanghoon; Cho, Sungwe; Do, Jung-Ho; Yang, Giyoung; Lim, Jinyoung, Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same.
  13. Song, Taejoong; Baek, Sanghoon; Cho, Sungwe; Do, Jung-Ho; Yang, Giyoung; Lim, Jinyoung, Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semicondutor device using the same.
  14. Gopalakrishnan, Prakash; Yurovsky, Alisa, Optimizing circuit layouts by configuring rooms for placing devices.
  15. Alpert, Charles J.; Li, Zhuo D.; Nam, Gi-Joon; Ramji, Shyam; Reddy, Lakshmi N.; Roy, Jarrod A.; Taghavi, Taraneh E.; Villarrubia, Paul G.; Viswanathan, Natarajan, Post-placement cell shifting.
  16. Alpert, Charles J; Li, Zhuo D; Nam, Gi-Joon; Ramji, Shyam; Reddy, Lakshmi N; Roy, Jarrod A; Taghavi, Taraneh E; Villarrubia, Paul G; Viswanathan, Natarajan, Post-placement cell shifting.
  17. Alley, Charles L.; Likovich, Robert B.; Mendenhall, Joseph D.; Winemiller, Chad E., Systems for using relative positioning in structures with dynamic ranges.
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