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A technique for reducing input currents associated with a comparator circuit during certain events includes minimizing bias currents associated with the comparator circuit when a magnitude of an input signal at a signal input of the comparator circuit is a predetermined value from a magnitude of a r

A technique for reducing input currents associated with a comparator circuit during certain events includes minimizing bias currents associated with the comparator circuit when a magnitude of an input signal at a signal input of the comparator circuit is a predetermined value from a magnitude of a reference signal applied to a reference input of the comparator circuit. The bias currents are increased when the magnitude of the input signal is within the predetermined value of the magnitude of the reference signal.

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1. A comparator circuit with controlled outer transistor stage bias currents, comprising:an outer transistor stage, including: a first transistor including a signal input terminal, a first output terminal and a second output terminal; and a second transistor including a reference input terminal, a f

1. A comparator circuit with controlled outer transistor stage bias currents, comprising:an outer transistor stage, including: a first transistor including a signal input terminal, a first output terminal and a second output terminal; and a second transistor including a reference input terminal, a first output terminal and a second output terminal, wherein the first and second output terminals of the first and second transistors are coupled across a power source, and wherein the first and second transistors of the outer transistor stage provide drive currents to transistors of an inner transistor stage; bias current control circuitry for controlling bias currents associated with the first and second transistors, wherein the bias current control circuitry minimizes the bias currents when a difference between a magnitude of an input signal at the signal input terminal and a magnitude of a reference signal applied to the reference input terminal is greater than a predetermined value, and wherein the bias current control circuitry increases the bias currents associated with the comparator circuit when the difference between the magnitude of the input signal at the signal input terminal and the magnitude of the reference signal at the reference input terminal is less than the predetermined value; and a blinding timer discharge current source configured to limit current drawn by a capacitor coupled to the input signal terminal being charged, wherein the blinding timer discharge current source is coupled across the capacitor. 2. The comparator circuit of claim 1, wherein the input and reference signals are voltage signals.3. The comparator circuit of claim 1, wherein the bias currents are increased to a maximum value when the difference between the magnitude of the input signal at the signal input terminal and the magnitude of the reference signal at the reference input terminal is less than the predetermined value.4. The comparator circuit of claim 1, wherein the bias currents are at a desired magnitude when the magnitudes of the input and reference signals are substantially equal.5. The comparator circuit of claim 1, wherein the signal input terminal is a non-inverting input and the reference input terminal is an inverting input.6. The comparator circuit of claim 1, wherein the predetermined value is about 50 mV.7. The comparator circuit of claim 1, wherein the transistors are bipolar transistors.8. A method for reducing input currents associated with a comparator circuit during certain events, comprising the steps of:minimizing bias currents associated with a comparator circuit when a difference between a magnitude of an input signal at a signal input of the comparator circuit and a magnitude of a reference signal applied to a reference input of the comparator circuit is greater than a predetermined value; increasing the bias currents associated with the comparator circuit when the magnitude of the input signal at the signal input of the comparator circuit and the magnitude of the reference signal at the reference input of the comparator circuit is less than the predetermined value; and coupling a blinding timer discharge current source across a capacitor operatively coupled to the comparator signal input and configuring said blinding timer discharge current source to limit current drawn thereby while said capacitor is being charged. 9. The method of claim 8, wherein the bias currents are applied to outer stage transistors of the comparator circuit.10. The method of claim 8, wherein the input and reference signals are voltage signals.11. The method of claim 8, wherein the bias currents are increased when the difference between the magnitude of the input signal at the signal input of the comparator circuit and the magnitude of the reference signal at the reference input of the comparator circuit is less than the predetermined value.12. The method of claim 8, wherein the bias currents are at a desired magnitude when the magnitudes of the input and reference signals are substantially equal.13. The method of claim 8, wherein the signal input is a non-inverting input and the reference input is an inverting input.14. The method of claim 8, wherein the predetermined value is about 50 mV.15. An automotive ignition system including a comparator circuit with controlled outer transistor stage bias currents, the comparator circuit comprising:an outer transistor stage, including: a first transistor including a signal input terminal, a first output terminal and a second output terminal; and a second transistor including a reference input terminal, a first output terminal and a second output terminal, wherein the first and second output terminals of the first and second transistors are coupled across a power source, and wherein the first and second transistors of the outer transistor stage provide drive currents to transistors of an inner transistor stage; bias current control circuitry for controlling bias currents associated with the first and second transistors, wherein the bias current control circuitry minimizes the bias currents when a difference between a magnitude of an input signal at the signal Input terminal and a magnitude of a reference signal applied to the reference input terminal is greater than a predetermined value, and wherein the bias current control circuitry increases the bias currents associated with the comparator circuit when the difference between the magnitude of the input signal at the signal input terminal and the magnitude of the reference signal at the reference input terminal is less than the predetermined value, where the bias currents are at a desired magnitude when the magnitudes of the input and reference signals are substantially equal; a capacitor coupled across the signal input terminal of the first transistor and a signal return line; a switch coupled across the capacitor; and a blinding timer discharge current source coupled to the signal input terminal of the transistor, wherein the blinding tinier discharge current source is configured to substantially reduce its leakage current when the switch is off. 16. The system of claim 15, wherein the signal input terminal is a non-inverting input and the reference input terminal is an inverting input.17. A comparator circuit with controlled outer transistor stage bias currents, comprising:an outer transistor stage, including: a first transistor including a signal input terminal, a first output terminal and a second output terminal; and a second transistor including a reference input terminal, a first output terminal and a second output terminal, wherein the first and second output terminals of the first and second transistors are coupled across a power source, and wherein the first and second transistors of the outer transistor stage provide drive currents to transistors of an inner transistor stage; and bias current control circuitry for controlling bias currents associated with the first and second transistors, wherein the bias current control circuitry minimizes the bias currents when a difference between a magnitude of an input signal at the signal input terminal and a magnitude of a reference signal applied to the reference input terminal is greater than a predetermined value, and wherein the bias current control circuitry increases the bias currents associated with the comparator circuit when the difference between the magnitude of the input signal at the signal input terminal and the magnitude of the reference signal at the reference input terminal is less than the predetermined value, wherein the signal input terminal includes an associated leakage current compensation circuit. 18. The comparator circuit of claim 17, wherein the input and reference signals are voltage signals.19. The comparator circuit of claim 17, wherein the bias currents are increased to a maximum value when the difference between the magnitude of the input signal at the signal input terminal and the magnitude of the reference signal at the reference input terminal is less than the predetermined value.20. The comparator circuit of claim 17, wherein the bias currents are at a desired magnitude when the magnitudes of the input and reference signals are substantially equal.21. The comparator circuit of claim 17, wherein the signal input terminal is a non-inverting input and the reference input terminal is an inverting input.22. The comparator circuit of claim 17, wherein the predetermined value is about 50 mV.23. The comparator circuit of claim 17, wherein the transistors are bipolar transistors.