초록 ▼

This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued

This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a L2 cache. A second synchronous form of a DCBT instruction is used to prefetch data from the L2 cache to the CRB in the main CPU, which will bypass the L1 data cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.

대표청구항 ▼

1. A method for prefetching data in a microprocessor having a cache hierarchy, the cache hierarchy comprising a cache reload buffer (CRB), an L1 cache, and an L2 cache, the method comprising the steps of:prefetching a stream of data into the L2 cache by using an asynchronous form of a data cache blo

1. A method for prefetching data in a microprocessor having a cache hierarchy, the cache hierarchy comprising a cache reload buffer (CRB), an L1 cache, and an L2 cache, the method comprising the steps of:prefetching a stream of data into the L2 cache by using an asynchronous form of a data cache block touch (DCBT) instruction; prefetching the data from the L2 cache directly to the CRB without storing the data in the L1 cache by using a synchronous form of a DCBT instruction; and retrieving the data from the CRB for processing. 2. The method of claim 1, wherein the CRB has a dual usage and is used to hold both normal cache reloads and prefetched cache lines.3. A computer program product for prefetching data in a microprocessor having a cache hierarchy, the cache hierarchy comprising a cache reload buffer (CRB), an L1 cache, and an L2 cache, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:computer program code for prefetching a stream of data into the L2 cache by using an asynchronous form of a data cache block touch (DCBT) instruction; computer program code for prefetching the data from the L2 cache directly to the CRB without storing the data in the L1 cache by using a synchronous form of a DCBT instruction; and computer program code for retrieving the data from the CRB for processing. 4. The computer program product of claim 3, wherein the CRB has a dual usage and is used to hold both normal cache reloads and prefetched cache lines.5. A microprocessor comprising:a cache reload buffer (CRB); an L2 cache coupled to the CRB, the CRB being configured for receiving one or more cache lines from the L2 cache, wherein a stream of data is prefetched into the L2 cache by using an asynchronous form of a data cache block touch (DCBT) instruction; an L1 cache coupled to the CRB, the CRB being configured for writing normal demand loads to the L1 cache and for bypassing the L1 cache for prefetch loads, wherein the data from the L2 cache is prefetched directly to the CRB without storing the data in the L1 cache by using a synchronous form of a DCBT instruction; and a general-purpose register file (GPR) coupled to the CRB for retrieving the data from the CRB for processing. 6. The microprocessor of claim 5, wherein the CRB has a dual usage and is used to hold both the normal demand loads and the prefetch loads.7. The microprocessor of claim 5, further comprising:a format multiplexer coupled to the CRB and the L1 cache for receiving the normal demand loads from the L1 cache and for receiving the prefetch loads from the CRB, the format multiplexer being coupled to the GPR to send the normal demand loads and the prefetch loads to the GPR.