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Semiconductor integrated circuit device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/40
출원번호 US-0362661 (2001-12-17)
우선권정보 JP-0161630 (2001-05-30); JP-0383728 (2000-12-18)
국제출원번호 PCT//JP01/11039 (2003-06-19)
§371/§102 date 20030619 (20030619)
국제공개번호 WO02//50898 (2002-06-27)
발명자 / 주소
  • Shinozaki, Masao
  • Nishimoto, Kenji
  • Akioka, Takashi
  • Kohara, Yutaka
  • Asari, Sanae
  • Miyata, Shusaku
  • Nakazato, Shinji
출원인 / 주소
  • Renesas Technology Corporation
  • Hitachi ULSI Systems Co., Ltd.
대리인 / 주소
    Reed Smith LLP
인용정보 피인용 횟수 : 93  인용 특허 : 9

초록

Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and

대표청구항

1. A semiconductor integrated circuit device comprising:a semiconductor substrate;circuit elements and wirings which are provided on one main surface of the semiconductor substrate and constitute a circuit;first and second electrodes provided on the one main surface and electrically connected to the

이 특허에 인용된 특허 (9)

  1. Morikawa, Takenori; Soda, Masaaki; Shioiri, Satomi, Clock identification and reproduction circuit.
  2. Iwabuchi Kaoru,JPX, Method of manufacturing a semiconductor device.
  3. Fujihira Mitsuaki (Yokohama JPX), Method of manufacturing semiconductor device.
  4. Brannon James H. (Wappingers Falls NY) Lankard ; Sr. John R. (Mahopac NY), Patterning of polyimide films with ultraviolet light.
  5. Kazutami Arimoto JP, Semiconductor chip scale package and ball grid array structures.
  6. Kurashima Yasumi (Tokyo JPX), Semiconductor device with airbridge interconnection.
  7. Muraki Takeshi,JPX ; Yuyama Takayuki,JPX, Semiconductor integrated circuit device.
  8. Fujimori Yasuhiko,JPX, Semiconductor memory device.
  9. Higdon William D. (Greentown IN) Mack Susan A. (Kokomo IN) Cornell Ralph E. (Kokomo IN), Solderable contacts for flip chip integrated circuit devices.

이 특허를 인용한 특허 (93)

  1. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  2. Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Li-Ren; Lo, Hsin-Jung, Chip package and method for fabricating the same.
  3. Lin, Mou-Shiung; Lin, I, Shih-Hsiung, Chip package having a chip combined with a substrate via a copper pillar.
  4. Chen, Ke-Hung; Lin, Shih-Hsiung; Lin, Mou-Shiung, Chip package with dam bar restricting flow of underfill.
  5. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Chip package with die and substrate.
  6. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  7. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
  8. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang; Lo, Hsin-Jung, Chip structure.
  9. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  10. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  11. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.
  12. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Cylindrical bonding structure and method of manufacture.
  13. Hashimoto, Nobuaki, Electronic component.
  14. Lee, Jin-Yaun; Lin, Mou-Shiung; Huang, Ching-Cheng, Integrated chip package structure using ceramic substrate and method of manufacturing the same.
  15. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using organic substrate and method of manufacturing the same.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Integrated chip package structure using silicon substrate and method of manufacturing the same.
  17. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  18. Lin, Mou-Shiung; Lee, Jin-Yuan, Integrated circuit and method for fabricating the same.
  19. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  20. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  21. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  22. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  23. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  24. Lin, Mou-Shiung; Lee, Jin-Yuan; Chou, Chien-Kang, Integrated circuit chips with fine-line metal and over-passivation metal.
  25. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  26. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  27. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  28. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  29. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.
  30. Ito,Daisuke; Kawahara,Toshimi, Manufacturing method of semiconductor device.
  31. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Method for fabricating chip package with die and substrate.
  32. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Method for fabricating circuit component.
  33. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  34. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.
  35. Takahashi, Noriyuki, Method of manufacturing a semiconductor device.
  36. Takahashi, Noriyuki, Method of manufacturing a semiconductor device.
  37. Takahashi, Noriyuki, Method of manufacturing a semiconductor device.
  38. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  39. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  40. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  41. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  42. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  43. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  44. Lin, Mou-Shiung; Peng, Bryan, Multiple chips bonded to packaging structure with low noise and multiple selectable functions.
  45. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  46. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection process and structures.
  47. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  48. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  49. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  50. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  51. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  52. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chip.
  53. Lin, Mou-Shiung; Lee, Jin-Yuan, Post passivation interconnection schemes on top of IC chips.
  54. Lin, Mou-Shiung, Post passivation interconnection schemes on top of the IC chips.
  55. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  56. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.
  57. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection structures.
  58. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  59. Huang, Ching-Cheng; Lin, Chuen-Jye; Lei, Ming-Ta; Lin, Mou-Shiung, Reliable metal bumps on top of I/O pads after removal of test probe marks.
  60. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  61. Lin, Mou-Shiung; Yen, Huei-Mei; Lo, Hsin-Jung; Chou, Chiu-Ming; Chen, Ke-Hung, Semiconductor chip with a bonding pad having contact and test areas.
  62. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  63. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
  64. Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Ching-San; Lin, Mou-Shiung, Semiconductor chip with passivation layer comprising metal interconnect and contact pads.
  65. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  66. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.
  67. Kanamori, Kohji, Semiconductor device.
  68. Kasai,Hideo, Semiconductor device.
  69. Kasai,Hideo, Semiconductor device.
  70. Yoshida, Takayuki; Kuwabara, Kimihito; Motofuji, Takuma; Fukuda, Toshiyuki, Semiconductor device.
  71. Komiya, Kunihiro, Semiconductor device comprising power elements in juxtaposition order.
  72. Yoshida, Takayuki; Kuwabara, Kimihito; Motofuji, Takuma; Fukuda, Toshiyuki, Semiconductor device having circuit blocks in a single crystal layer, and bumps on certain blocks.
  73. Yilmaz, Hamza; Sapp, Steven; Wang, Qi; Li, Minhua; Murphy, James J.; Diroll, John Robert, Semiconductor die packages using thin dies and metal substrates.
  74. Shimizu, Yuui; Inoue, Satoshi, Semiconductor memory device and method of testing the same.
  75. Lee, Jong-joo, Semiconductor package.
  76. Lin, Mou-Shiung; Lee, Jin-Yuan; Huang, Ching-Cheng, Semiconductor package with interconnect layers.
  77. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.
  78. Chou, Chiu-Ming; Lin, Mou-Shiung, Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures.
  79. Lee, Jin-Yuan; Lin, Mou-Shiung, Structure of high performance combo chip and processing method.
  80. Uda,Kenichiro, Structure of power supply path utilized in design of integrated circuit.
  81. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  82. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  83. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  84. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  85. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  86. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  87. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  88. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  89. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  90. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  91. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  92. Young, Brian D., Trace routing within a semiconductor package substrate.
  93. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
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