초록

A chip scale package and a method for its manufacture which include providing sticky interconnects on a surface of a semiconductor die, the interconnects being surrounded by a layer of thermal epoxy.

대표청구항 ▼

1. A semiconductor device, comprising:a semiconductor die having a major surface; an electrical contact on said major surface of said semiconductor die; an interconnect on said electrical contact, said interconnect being composed of a sticky epoxy containing conductive particles; and a layer of ther

1. A semiconductor device, comprising:a semiconductor die having a major surface; an electrical contact on said major surface of said semiconductor die; an interconnect on said electrical contact, said interconnect being composed of a sticky epoxy containing conductive particles; and a layer of thermal epoxy disposed on said major surface and surrounding said interconnect. 2. A semiconductor device according to claim 1, wherein said layer of thermal epoxy has a maximum height below that of said interconnect.3. A semiconductor device according to claim 1, wherein said conductive particles comprise of silver.4. A semiconductor device according to claim 1, wherein said conductive epoxy comprises of 60% to 85% silver particles by weight, said particles being 3 to 40 microns.5. A semiconductor device according to claim 1, wherein all major electrical contacts of said die are disposed on said major surface, and wherein interconnects are formed on all major electrical contacts of said die.6. A semiconductor device according to claim 5, wherein said die is one of MOSFET, IGBT and diode.7. A semiconductor device according to claim 1, wherein said die is one of MOSFET, IGBT and diode.8. A semiconductor device, comprising:a semiconductor die having a major surface; an electrical contact on said major surface of said semiconductor die; an electrical interconnect comprised of an epoxy containing conductive particle and disposed on said electrical contact; and a layer of underfilling material disposed on said electrical contact around said electrical interconnect, said underfilling material being comprised of an uncured curable material. 9. A semiconductor device according to claim 8, wherein said underfilling material is a thermal epoxy.10. A semiconductor device according to claim 8, wherein said particles are 3 to 40 microns.11. A semiconductor device according to claim 8, wherein said conductive particles are comprised of silver.12. A semiconductor device according to claim 8, wherein all major electrical contacts of said die are disposed on said major surface, and wherein interconnects are formed on all major electrical contacts of said die.13. A semiconductor device according to claim 8, wherein said die is one of MOSFET, IGBT and diode.14. A semiconductor device comprising:a semiconductor die having at least one major electrode disposed on a major surface thereof; an electrical connector formed on said major electrode, said electrical connector being adapted for electrical connection to a conductive pad; and an underfilling body disposed on said one major electrode, said underfilling body being adapted to become disposed between said electrode and a circuit board when said device is mounted on said circuit board wherein said major electrode is a power electrode of said semiconductor die. 15. A semiconductor device according to claim 14, wherein said underfilling body is comprised of a curable epoxy.16. A semiconductor device according to claim 15, wherein said epoxy is thermally curable.17. A semiconductor device according to claim 14, wherein said semiconductor die is a power MOSFET.