IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0846119
(2001-04-30)
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발명자
/ 주소 |
- Gilboa, Yitzhak
- Koutny, Jr., William W. C.
- Hedayati, Steven
- Ramkumar, Krishnaswamy
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출원인 / 주소 |
- Cypress Semiconductor Corp.
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
3 인용 특허 :
107 |
초록
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A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not inclu
A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.
대표청구항
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1. A method for fabricating a shallow trench isolation region, comprising:forming an intermediate layer upon an upper surface of a semiconductor topography, wherein the intermediate layer comprises a doped oxide layer;forming one or more trenches within the intermediate layer and the semiconductor t
1. A method for fabricating a shallow trench isolation region, comprising:forming an intermediate layer upon an upper surface of a semiconductor topography, wherein the intermediate layer comprises a doped oxide layer;forming one or more trenches within the intermediate layer and the semiconductor topography;blanket depositing a trench fill material over and within the one or more trenches;polishing the trench fill material with an abrasive polishing surface in the absence of a fluid or in the presence of a fluid that is substantially free of particulate matter to form an upper surface at an elevation above the trenches, wherein the upper surface does not comprise a polish stop material; andetching an entirety of the upper surface simultaneously, wherein remaining portions of the trench fill material are laterally confined within the trenches.2. The method of claim 1, wherein an tipper surface of the remaining portions is above an upper surface of a semiconductor substrate within the semiconductor topography.3. The method of claim 2, wherein said upper surface of the remaining portions is less than approximately 200 angstroms above the tipper surface of the semiconductor substrate.4. The method of claim 1, wherein the step of polishing comprises inserting a fluid consisting essentially of water between the trench fill material and the abrasive polishing surface.5. The method of claim 1, wherein said etching comprises etching at least a portion of the doped oxide layer.6. The method of claim 1, wherein said intermediate layer further comprises a base oxide layer.7. The method of claim 1, wherein said doped oxide layer comprises borophosphosilicate glass.8. The method of claim 1, wherein said intermediate layer further comprises a nitride layer, and wherein a thickness of said nitride layer is less than approximately 500 angstroms.9. A method for processing a semiconductor topography, comprising:polishing an upper layer of said semiconductor topography with an abrasive polishing surface in the presence of a fluid that is substantially free of particulate matter to form an upper surface of the semiconductor topography at an elevation above an underlying layer, wherein the underlying layer comprises a lateral variation in polishing characteristics, and wherein the step of polishing comprises inserting a fluid consisting essentially of water between the semiconductor topography and the abrasive polishing surface; andetching the entirety of the upper surface of the semiconductor topography simultaneously to expose the underlying layer.10. The method of claim 9, wherein said upper surface of the semiconductor topography is spaced sufficiently above the underlying layer to avoid dishing during said polishing.11. The method of claim 9, wherein said upper surface of the semiconductor topography is spaced sufficiently above the underlying layer to avoid polishing the underlying layer.12. The method of claim 9, wherein said elevation is between approximately 100 angstroms and approximately 1000 angstroms.13. The method of claim 9, wherein said upper layer comprises an interlevel dielectric layer.14. The method of claim 13, wherein said interlevel dielectric layer comprises silicon dioxide.15. The method of claim 9, wherein said underlying layer comprises a silicon substrate patterned with dielectric filled trenches.16. The method of claim 9, further comprising:forming an intermediate layer upon an upper surface of the semiconductor topography;forming one or more trenches within the intermediate layer and the semiconductor topography; andblanket depositing the upper layer over and within the one or more trenches prior to the step of polishing the upper layer.17. The method of claim 16, wherein the intermediate layer comprises a doped oxide layer.18. The method of claim 17, wherein said doped oxide layer comprises borophosphosilicate glass.19. The method of claim 16, wherein said intermediate layer comprises a nitride layer with a thickness of less than approximately 500 angstroms.20. The method of claim 16, wherein said intermediate layer further comprises a silicon carbide layer.21. The method of claim 16, wherein said intermediate layer further comprises a carbonated polymer layer.22. A method for fabricating a shallow trench isolation region, comprising:forming an oxide layer upon and in contact with a substrate comprising silicon;forming one or more trenches within the oxide layer and the substrate;blanket depositing a fill material within the one or more trenches and upon and in contact with remaining portions of the oxide layer;polishing the fill material with an abrasive polishing surface in the absence of a fluid or in the presence of a fluid that is substantially free of particulate matter to form a substantially planar surface at an elevation above an uppermost surface of the substrate; andetching an entirety of the substantially planar surface simultaneously to expose the substrate.23. The method of claim 22, wherein the step of forming the oxide layer comprises growing the oxide layer by thermal oxidation of the substrate.24. The method of claim 22, wherein the step of forming the oxide layer comprises depositing the oxide layer by chemical vapor deposition techniques.25. The method of claim 22, wherein the oxide layer consists essentially of silicon oxide.26. The method of claim 22, wherein the oxide layer consists essentially of siliconoxynitride.27. The method of claim 22, wherein said elevation is between approximately 100 angstroms and approximately 1000 angstroms above the uppermost surface of the substrate.28. The method of claim 22, wherein the stop of forming the oxide layer comprises forming the oxide layer to have a thickness between approximately 50 angstroms and approximately 250 angstroms.29. The method of claim 22, wherein the step of polishing comprises inserting a fluid consisting essentially of water between the fill material and the abrasive polishing surface.30. The method of claim 22, wherein the step of polishing comprises polishing at least a portion of the oxide layer.
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