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Method of electroless introduction of interconnect structures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0753256 (2000-12-28)
발명자 / 주소
  • Dubin, Valery M.
  • Thomas, Christopher D.
  • McGregor, Paul
  • Datta, Madhav
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor &
인용정보 피인용 횟수 : 28  인용 특허 : 31

초록

A method comprising introducing an interconnect structure in an opening through a dielectric over a contact point, and introducing a conductive shunt material through a chemically-induced oxidation-reduction reaction. A method comprising introducing an interconnect structure in an opening through a

대표청구항

1. A method comprising:introducing a barrier material in an opening through a dielectric over a contact point; introducing a conductive shunt material on the barrier material through a chemically-induced oxidation-reduction reaction; forming an interconnect structure in the opening over the conducti

이 특허에 인용된 특허 (31)

  1. Shacham Yosef Y. (Ithaca NY) Bielski Roman (Ithaca NY), Alkaline free electroless deposition.
  2. Kakizawa Masahiko,JPX ; Umekita Ken-ichi,JPX ; Hayashida Ichiro,JPX, Cleaning agent for a semi-conductor substrate.
  3. Hsiung Chiung-Sheng,TWX ; Hsieh Wen-Yi,TWX ; Lur Water,TWX, Copper damascene technology for ultra large scale integration circuits.
  4. Wagner Bernhard,DEX ; Van Der Broeck Heinz,DEX, DC/AC converter with equally loaded switches.
  5. James A. Cunningham, Diffusion barriers for copper interconnect systems.
  6. Edelstein Daniel C. ; Dalton Timothy J. ; Gaudiello John G. ; Krishnan Mahadevaiyer ; Malhotra Sandra G. ; McGlashan-Powell Maurice ; O'Sullivan Eugene J. ; Sambucetti Carlos J., Dual etch stop/diffusion barrier for damascene interconnects.
  7. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  8. Kumasaka Osamu (Yamanashi JPX) Yamaoka Nobuki (Yamanashi JPX), Electroless plating method and apparatus.
  9. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  10. Simpson Cindy Reidsema, Interconnect structure in a semiconductor device and method of formation.
  11. Smith ; deceased Peter H. (late of Anchorage KY by Pamela S. Smith ; executor), Magnetron with full wave bridge inverter.
  12. DeLuca Michael A. (Holbrook NY) McCormack John F. (Roslyn Heights NY), Metallization of ceramics.
  13. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  14. Chow Melanie M. (Poughquag NY) Cronin John E. (Milton VT) Guthrie William L. (Hopewell Junction NY) Kaanta Carter W. (Essex Junction VT) Luther Barbara (Devon PA) Patrick William J. (Newburgh NY) Per, Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive line.
  15. Steven C. Avanzino ; Kai Yang ; Sergey Lopatin ; Todd P. Lukanc, Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film.
  16. Hsu Shih-Ying,TWX, Method of fabricating metal interconnect.
  17. Orita, Toshiyuki, Method of forming a via hole in a semiconductor device.
  18. Daniel C. Edelstein ; Timothy J. Dalton ; John G. Gaudiello ; Mahadevaiyer Krishnan ; Sandra G. Malhotra ; Maurice McGlashan-Powell ; Eugene J. O'Sullivan ; Carlos J. Sambucetti, Method of forming barrier layers for damascene interconnects.
  19. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
  20. Leu, Jihperng; Thomas, Christopher D., Method of making semiconductor device using an interconnect.
  21. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  22. Furuhashi Naoki,JPX ; Yamaguchi Shuuji,JPX, Power supply circuit utilizing a piezoelectric transformer that supplies power to a load whose impedance varies depending on temperature.
  23. Gilton Terry L. (Boise ID) Tuttle Mark E. (Boise ID) Cathey David A (Boise ID), Process for metallizing integrated circuits with electrolytically-deposited copper.
  24. Hussein Makarem A., Process to manufacture continuous metal interconnects.
  25. Chao-Kun Hu ; Robert Rosenberg ; Judith Marie Rubino ; Carlos Juan Sambucetti ; Anthony Kendall Stamper, Reduced electromigration and stressed induced migration of Cu wires by surface coating.
  26. Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
  27. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  28. Nakano, Hiroshi; Itabashi, Takeyuki; Akahoshi, Haruo, Semiconductor device having cobalt alloy film with boron.
  29. Hoshino Kazuhiro (Tokyo JPX), Semiconductor device using copper metallization.
  30. Uzoh Cyprian E., Triple damascence tungsten-copper interconnect structure.
  31. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (28)

  1. Ivanov, Igor C., Barrier layer configurations and methods for processing microelectronic topographies having barrier layers.
  2. Yakobson,Eric; Hurtubise,Richard; Witt,Christian; Chen,Qingyun, Capping of metal interconnects in integrated circuit electronic devices.
  3. Chen,Ling; Chang,Mei, Deposition processes for tungsten-containing barrier layers.
  4. Johnston, Steven W.; Dubin, Valery M.; McSwiney, Michael L.; Moon, Peter, Forming a copper diffusion barrier.
  5. Johnston,Steven W.; Dubin,Valery M.; McSwiney,Michael L.; Moon,Peter, Forming a copper diffusion barrier.
  6. Chopra, Dinesh, Method and apparatus for simultaneously removing multiple conductive materials from microelectronic substrates.
  7. Lee, Whonchee; Meikle, Scott G.; Blalock, Guy T., Method for forming a microelectronic structure having a conductive material and a fill material with a hardness of 0.04 GPA or higher within an aperture.
  8. Lee, Whonchee; Meikle, Scott G.; Blalock, Guy T., Method for removing metal layers formed outside an aperture of a BPSG layer utilizing multiple etching processes including electrochemical-mechanical polishing.
  9. Lee, Whonchee; Moore, Scott E.; Meikle, Scott G., Method for selectively removing conductive material from a microelectronic substrate.
  10. Lee, Whonchee; Meikle, Scott G.; Moore, Scott E.; Doan, Trung T., Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate.
  11. Lee, Whonchee; Moore, Scott E.; Meikle, Scott G., Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or polishing medium.
  12. Lee, Whonchee; Moore, Scott E.; Meikle, Scott G., Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate.
  13. Lee, Whonchee; Moore, Scott E.; Meikle, Scott G., Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate.
  14. Lee, Whonchee; Moore, Scott E.; Vaartstra, Brian A., Methods and apparatus for removing conductive material from a microelectronic substrate.
  15. Lee, Whonchee; Moore, Scott E.; Meikle, Scott G., Methods and apparatus for selectively removing conductive material from a microelectronic substrate.
  16. Lee, Whonchee, Methods and apparatuses for electrochemical-mechanical polishing.
  17. Lee, Whonchee, Methods and apparatuses for electrochemical-mechanical polishing.
  18. Lee, Whonchee; Sabde, Gundu M., Methods and systems for removing materials from microfeature workpieces with organic and/or non-aqueous electrolytic media.
  19. Lee, Whonchee; Sabde, Gundu M., Methods and systems for removing materials from microfeature workpieces with organic and/or non-aqueous electrolytic media.
  20. Stephanou, Philip Jason; Burns, David William; Shenoy, Ravindra V., Microspeaker with piezoelectric, metal and dielectric membrane.
  21. Cheng,Chin Chang; Dubin,Valery M., Multiple stage electroless deposition of a metal layer.
  22. Stephanou, Philip Jason; Burns, David William, Piezoelectric microphone fabricated on glass.
  23. Stephanou, Philip Jason; Burns, David William, Piezoelectric microphone fabricated on glass.
  24. Yang, Chih-Chao; Gaudet, Simon; Lavoie, Christian; Ponoth, Shom; Spooner, Terry A., Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement.
  25. Yang,Chih Chao; Gaudet,Simon; Lavoie,Christian; Ponoth,Shom; Spooner,Terry A., Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement.
  26. Yang,Chih Chao; Gaudet,Simon; Lavoie,Christian; Ponoth,Shom; Spooner,Terry A., Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement.
  27. Ivanov, Igor C., Systems and methods affecting profiles of solutions dispensed across microelectronic topographies during electroless plating processes.
  28. Stephanou, Philip Jason; Burns, David William; Shenoy, Ravindra V., Transducer with piezoelectric, conductive and dielectric membrane.
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